BIOS:(BASIC INPUT/OUTPUT SYSTEM), optimization, common terms explained.

TURINYS

ABOUT BIOS 6
How BIOS Works 6
What BIOS Does 6
Booting the Computer 8
Configuring BIOS 9
Updating Your BIOS 10
Bootstrap Management 11
Boot Other Device 11
Boot Sequence 11
Boot Sequence EXT Means 12
Boot To OS/2 12
Boot Up Floppy Seek 12
Boot Up NumLock Status 13
Delay IDE Initial 13
First Boot Device 14
Init Display First 14
Primary Graphics Adapter 15
Primary VGA BIOS 15
Quick Boot 16
Quick Power On Self Test 16
Report No FDD For Win95 17
Reset Configuration Data 17
Resource Controlled By 18
Second Boot Device 18
Third Boot Device 19
Graphics Subsystem 19
AGP 2X Mode 19
AGP 4X Drive Strength 20
AGP 4X Mode 20
AGP 8X Mode 20
AGP Always Compensate 21
AGP Aperture Size 21
AGP Clock / CPU FSB Clock 22
AGP Drive Strength 22
AGP Drive Strength N Ctrl 23
AGP Drive Strength P Cttrl 23
AGP Driving Control 24
AGP Driving Value 24
AGP Fast Write 25
AGP ISA Aliasing 25
AGP Master 1WS Read 25
AGP Master 1WS Write 26
AGP Prefetch 26
AGP Secondary Lat Timer 26
AGP Spread Spectrum 27
AGP to DRAM Prefetch 28
AGPCLK / CPUCLK 28
DBI Output for AGP Trans. 28
Graphic Win Size 29
No Mask of SBA FE 30
PCI/VGA Palette Snoop 30
Post Write Combine 31
USWC Write Posting 31
Video BIOS Cacheable 32
Video BIOS Shadowing 33
Video Memory Cache Mode 34
Video RAM Cacheable 34
Memory Subsystem 35
Act Bank A to B CMD Delay 35
Delay DRAM Read Latch 36
DRAM Act to PreChrg CMD 37
DRAM Data Integrity Mode 37
DRAM Idle Timer 38
DRAM Interleave Time 38
DRAM PreChrg to Act CMD 39
DRAM Ratio (CPU:DRAM) 39
DRAM Ratio H/W Strap 40
DRAM Reead Latch Delay 41
DRAM Refresh Rate 42
Fast R-W Turn Around 42
Force 4-Way Interleave 42
Gate A20 Option 43
MD Driving Strength 44
Memory Hole At 15M-16M 44
OS Select For DRAM > 64MB 45
OS/2 Onboard Memory > 64M 45
Read-Around-Write 46
Read Wait State 46
Refresh Interval 47
Refresh Mode Select 47
SDRAM 1T Command 48
SDRAM 1T Command Control 48
SDRAM Bank Interleave 49
SDRAM Burst Len 50
SDRAM Bu

urst Length 50
SDRAM CAS Latency Time 50
SDRAM Command Rate 51
SDRAM Cycle Length 51
SDRAM Cycle Time Tras/Trc 52
SDRAM Idle Limit 52
SDRAM RAS Precharge Time 53
SDRAM RAS Pulse Width 53
SDRAM RAS-to-CAS Delay 54
SDRAM Row Active Time 54
SDRAM Tras Timing Value 55
SDRAM Trp Timing Value 55
Super Bypass Mode 56
Super Bypass Wait State 56
SuperStability Mode 57
Miscellaneous 58
Anti-Virus Protection 58
Duplex Select 58
Flash BIOS Protection 59
Floppy 3 Mode Support 59
Hardware Reset Protect 59
KBC Input Clock Select 60
Onboard IR Function 60
Onboard Parallel Port 60
Onboard Serial Port 1 61
Onboard Serial Port 2 61
Onboard USB Controller 62
Parallel Port Mode 62
Power On Function 63
RxD, TxD Active 63
Security Setup 64
Spread Spectrum 64
USB Controller 65
Virus Warning 65
Processor 66
Athlon 4 SSED Instruction 66
Auto Turn Off PCI Clock Pin 66
Clock Throttle 67
Compatible FPU OPCODE 67
CPU Drive Strength 68
CPU Fast String 68
CPU Hyper-Threading 68
CPU L2 Cache ECC Checking 69
CPU Level 1 Cache 69
CPU Level 2 Cache 70
CPU Level 3 Cache 70
CPU Thermal-Throttling 71
CPU VCore Voltage 71
Delay Prior To Thermal 72
FPU OPCODE Compatible Mode 73
Host Bus In-Order Queue Depth 73
Hyper-Threading Technology 74
In-Order Queue Depth 74
IOQD 75
K7 CLK_CTL Select 76
L3 Cache 77
Level 2 Cache Latency 77
N/B Strap CPU As 78
Processor Number Feeature 79
S2K Bus Driving Strength 79
S2K Strobe N Control 80
S2K Strobe P Control 80
Speed Error Hold 81
Storage Subsystem 81
32-bit Disk Access 81
32-bit Transfer Mode 82
ATA100RAID IDE Controller 82
HDD S.M.A.R.T. Capability 82
IDE Bus Master Support 83
IDE HDD Block Mode 84
Master Drive PIO Mode 84
Master Drive UltraDMA 85
Onboard FDD Controller 86
Onboard IDE-1 Controller 86
Onboard IDE-2 Controller 87
PCI IDE Busmaster 87
Swap Floppy Drive 88
System Bus 88
16-bit I/O Recovery Time 88
8-bit I/O Recovery Time 89
AT Bus Clock 89
Auto Detect DIMM/PCI Clk 90
Byte Merge 90
CPU to PCI Post Write 90
CPU to PCI Write Buffer 91
Delayed Transaction 91
Disable Unused PCI Clock 92
FSB Spread Spectrum 92
ISA 14.318MHz Clock 93
ISA Enable Bit 93
Master Priority Rotation 94
P2C/C2P Concurrency 94
Passive Release 95
PCI 2.1 Compliance 95
PCI Chaining 96
PCI Clock /
CPU FSB Clock 97
PCI Delay Transaction 98
PCI Dynamic Bursting 99
PCI IRQ Activated By 99
PCI Latency Timer 100
PCI Master 0 WS Read 100
PCI Master 0 WS Write 101
PCI Master Read Caching 101
PCI Pipelining 101
PCI Prefetch 102
PCI Target Latency 102
PCI to DRAM Prefetch 103
PCI#2 Access #1 Retry 103
Split Lock Operations 104
Synchronouse Mode Select 104
VLink 8X Support 104
System Resource Management 105
APIC Function 105
Assign IRQ For USB 105
Assign IRQ For VGA 106
ECP Mode Use DMA 106
EPP Mode Select 106
Force Update ESCD 107
Interrupt Mode 107
MPS Control Version For OS 108
MPS Revision 108
PIRQ x Use IRQ No. 109
PNP OS Installed 109

ABOUT BIOS

How BIOS Works

One of the most common uses of Flash memory is for the basic input/output system of your computer, commonly known as the BIOS (pronounced “bye-ose”). On virtually every computer available, the BIOS makes sure all the other chips, hard drives, ports and CPU function together.
Every desktop and laptop computer in common use today contains a microprocessor as its central processing unit. The microprocessor is the hardware component. To get its work done, the microprocessor executes a set of instructions known as software (see How Microprocessors Work for details). You are probably very familiar with two different types of software:
• The operating system – The operating system provides a set of services for the applications running on your computer, and it also provides the fundamental user interface for your computer. Windows 98 and Linux are examples of

f operating systems. (See How Operating Systems Work for lots of details.)
• The applications – Applications are pieces of software that are programmed to perform specific tasks. On your computer right now you probably have a browser application, a word processing application, an e-mail application and so on. You can also buy new applications and install them.
It turns out that the BIOS is the third type of software your computer needs to operate successfully. In this article, you’ll learn all about BIOS — what it does, how to configure it and what to do if your BIOS needs updating.

What BIOS Does

The BIOS software has a number of different roles, but its most important role is to load the operating system. When you turn on your computer and the microprocessor tries to execute its first instruction, it has to get that instruction from somewhere. It cannot get it from the operating system because the operating system is located on a hard disk, and the microprocessor cannot get to it without some instructions that tell it how. The BIOS provides those instructions. Some of the other common tasks that the BIOS performs include:
• A power-on self-test (POST) for all of the different ha

ardware components in the system to make sure everything is working properly
• Activating other BIOS chips on different cards installed in the computer – For example, SCSI and graphics cards often have their own BIOS chips.
• Providing a set of low-level routines that the operating system uses to interface to different hardware devices – It is these routines that give the BIOS its name. They manage things like the keyboard, the screen, and the serial and parallel ports, especially when the computer is booting.
• Managing a collection of settings for the hard disks, clock, etc.
The BIOS is special software that interfaces the major hardware components of your computer with the operating system. It is usually stored on a Flash memory chip on the motherboard, but sometimes the chip is another type of ROM.

BIOS uses Flash memory, a type of ROM.
When you turn on your computer, the BIOS does several things. This is its usual sequence:
1. Check the CMOS Setup for custom settings
2. Load the interrupt handlers and device drivers
3. Initialize registers and power management
4. Perform the power-on self-test (POST)
5. Display system settings
6. Determine which devices are bootable
7. Initiate the bootstrap sequence
The first thing the BIOS does is check the information stored in a tiny (64 bytes) amount of RAM located on a complementary metal oxide semiconductor (CMOS) chip. The CMOS Setup provides detailed information particular to your system and can be altered as your system changes. The BIOS uses this information to modify or supplement its default programming as needed. We will talk more about these settings later.
Interrupt handlers are small pieces of software that act as translators between the hardware components and the operating system. For example, when you press a key on your keyboard, the signal is sent to the keyboard interrupt handler, which tells the CPU what it is and passes it on to the operating system. The device drivers are other pieces of software that identify the base hardware components such as keyboard, mouse, hard drive and floppy drive. Since the BIOS is constantly intercepting signals to and from the hardware, it is usually copied, or shadowed, into RAM to run faster.
Booting the Computer

Whenever you turn on your computer, the first thing you see is the BIOS software doing its thing. On many machines, the BIOS displays text describing things like the amount of memory installed in your computer, the type of hard disk and so on. It turns out that, during this boot sequence, the BIOS is doing a remarkable amount of work to get your computer ready to run. This section briefly describes some of those activities for a typical PC.
After checking the CMOS Setup and loading the interrupt handlers, the BIOS determines whether the video card is operational. Most video cards have a miniature BIOS of their own that initializes the memory and graphics processor on the card. If they do not, there is usually video driver information on another ROM on the motherboard that the BIOS can load.
Next, the BIOS checks to see if this is a cold boot or a reboot. It does this by checking the value at memory address 0000:0472. A value of 1234h indicates a reboot, and the BIOS skips the rest of POST. Anything else is considered a cold boot.
If it is a cold boot, the BIOS verifies RAM by performing a read/write test of each memory address. It checks the PS/2 ports or USB ports for a keyboard and a mouse. It looks for a peripheral component interconnect (PCI) bus and, if it finds one, checks all the PCI cards. If the BIOS finds any errors during the POST, it will notify you by a series of beeps or a text message displayed on the screen. An error at this point is almost always a hardware problem.
The BIOS then displays some details about your system. This typically includes information about:
• The processor
• The floppy drive and hard drive
• Memory
• BIOS revision and date
• Display

Any special drivers, such as the ones for small computer system interface (SCSI) adapters, are loaded from the adapter, and the BIOS displays the information. The BIOS then looks at the sequence of storage devices identified as boot devices in the CMOS Setup. “Boot” is short for “bootstrap,” as in the old phrase, “Lift yourself up by your bootstraps.” Boot refers to the process of launching the operating system. The BIOS will try to initiate the boot sequence from the first device. If the BIOS does not find a device, it will try the next device in the list. If it does not find the proper files on a device, the startup process will halt. If you have ever left a floppy disk in the drive when you restarted your computer, you have probably seen this message.

This is the message you get if a floppy disk is in the drive when you restart your computer.
The BIOS has tried to boot the computer off of the floppy disk left in the drive. Since it did not find the correct system files, it could not continue. Of course, this is an easy fix. Simply pop out the disk and press a key to continue.
Configuring BIOS

In the previous list, you saw that the BIOS checks the CMOS Setup for custom settings. Here’s what you do to change those settings.
To enter the CMOS Setup, you must press a certain key or combination of keys during the initial startup sequence. Most systems use “Esc,” “Del,” “F1,” “F2,” “Ctrl-Esc” or “Ctrl-Alt-Esc” to enter setup. There is usually a line of text at the bottom of the display that tells you “Press ___ to Enter Setup.”
Once you have entered setup, you will see a set of text screens with a number of options. Some of these are standard, while others vary according to the BIOS manufacturer. Common options include:
• System Time/Date – Set the system time and date
• Boot Sequence – The order that BIOS will try to load the operating system
• Plug and Play – A standard for auto-detecting connected devices; should be set to “Yes” if your computer and operating system both support it
• Mouse/Keyboard – “Enable Num Lock,” “Enable the Keyboard,” “Auto-Detect Mouse”.
• Drive Configuration – Configure hard drives, CD-ROM and floppy drives
• Memory – Direct the BIOS to shadow to a specific memory address
• Security – Set a password for accessing the computer
• Power Management – Select whether to use power management, as well as set the amount of time for standby and suspend
• Exit – Save your changes, discard your changes or restore default settings

CMOS Setup
Be very careful when making changes to setup. Incorrect settings may keep your computer from booting. When you are finished with your changes, you should choose “Save Changes” and exit. The BIOS will then restart your computer so that the new settings take effect.
The BIOS uses CMOS technology to save any changes made to the computer’s settings. With this technology, a small lithium or Ni-Cad battery can supply enough power to keep the data for years. In fact, some of the newer chips have a 10-year, tiny lithium battery built right into the CMOS chip!
Updating Your BIOS

Occasionally, a computer will need to have its BIOS updated. This is especially true of older machines. As new devices and standards arise, the BIOS needs to change in order to understand the new hardware. Since the BIOS is stored in some form of ROM, changing it is a bit harder than upgrading most other types of software.
To change the BIOS itself, you’ll probably need a special program from the computer or BIOS manufacturer. Look at the BIOS revision and date information displayed on system startup or check with your computer manufacturer to find out what type of BIOS you have. Then go to the BIOS manufacturer’s Web site to see if an upgrade is available. Download the upgrade and the utility program needed to install it. Sometimes the utility and update are combined in a single file to download. Copy the program, along with the BIOS update, onto a floppy disk. Restart your computer with the floppy disk in the drive, and the program erases the old BIOS and writes the new one. You can find a BIOS Wizard that will check your BIOS at BIOS Upgrades.

Major BIOS manufacturers include:
• American Megatrends Inc. (AMI)
• Phoenix Technologies
• ALi
• Winbond
As with changes to the CMOS Setup, be careful when upgrading your BIOS. Make sure you are upgrading to a version that is compatible with your computer system. Otherwise, you could corrupt the BIOS, which means you won’t be able to boot your computer. If in doubt, check with your computer manufacturer to be sure you need to upgrade.

Bootstrap Management

Boot Other Device
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the BIOS will attempt to load an operating system from the Second Boot Device or Third Boot Device if it fails to load one from the First Boot Device.
This feature is enabled by default and it is recommended that you leave it as such.
Boot Sequence
Common Options : A, C, SCSI

C, A, SCSI

C, CD-ROM, A

CD-ROM, C, A

D, A, SCSI (only when you have at least 2 IDE hard disks)

E, A, SCSI (only when you have at least 3 IDE hard disks)

F, A, SCSI (only when you have 4 IDE hard disks)

SCSI, A, C

SCSI, C, A

A, SCSI, C

LS/ZIP, C
Quick Review
This BIOS feature enables you to set the sequence by which the BIOS will search for an operating system during the boot-up process. To ensure the shortest booting time possible, set the hard disk that contains your operating system as the first choice. Normally, this would be drive C for IDE drives but if you are using a SCSI hard disk, then select SCSI.
Some motherboards have an external (not part of the chipset) IDE controller. In such motherboards, the SCSI option is replaced with an EXT option. If you want to boot from an IDE hard disk running off the internal IDE controller, do not set the Boot Sequence to start with EXT. Please note that this feature works in conjunction with the Boot Sequence EXT Means feature.

Boot Sequence EXT Means
Common Options : IDE, SCSI
Quick Review
This BIOS feature determines whether the system boots from an IDE hard disk connected to an external IDE controller or a SCSI hard disk. However, it will only have an effect if the EXT option had been selected in the Boot Sequence feature.
To boot from an IDE hard disk that’s connected to the external IDE controller, you must set this feature to IDE.
In order to boot from a SCSI hard disk, you must set this feature to SCSI.
Boot To OS/2
Common Options : Yes, No
Quick Review
This is similar to the OS Select For DRAM > 64M BIOS feature.
This BIOS feature determines how systems with more than 64MB of memory are managed. A wrong setting can cause problems like erroneous memory detection.
If you are using an older version of the IBM OS/2 operating system, you should select Yes.
If you are using the IBM OS/2 Warp v3.0 or higher operating system, you should select No.
If you are using an older version of the IBM OS/2 operating system but have already installed all the relevant IBM FixPaks, you should select No.
Users of non-OS/2 operating systems (like Microsoft Windows XP) should select the No option.
Boot Up Floppy Seek
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the BIOS checks for a floppy drive during boot-up or not.
If enabled, the BIOS will attempt to detect and initialize the floppy drive. If it cannot detect one, it will flash an error message. However, the system will still be allowed to continue the boot process.
If this feature is disabled, the BIOS will skip the floppy drive check. This speeds up the booting process by several seconds.
Since a floppy drive check is really pointless, it is recommended that you disable this feature for a faster booting process.
Boot Up NumLock Status
Common Options : On, Off
Quick Review
This BIOS feature sets the input mode of the numeric keypad at boot up.
If you turn this feature on, the BIOS will set the numeric keypad to function in the numeric mode.
If you set it to Off, the numeric keypad will function in the cursor control mode instead.
The numeric keypad’s input mode can be switched to either numeric or cursor control mode and back again at any time after boot up.
The choice of initial keypad input mode is entirely up to your preference.
Delay IDE Initial
Common Options : 0 to 15
Quick Review
Motherboards are capable of booting up much faster these days. Therefore, initialization of IDE devices now take place much earlier. Unfortunately, this also means that some older IDE drives will not be able to spin up in time to be initialized! When this happens, the BIOS will not be able to detect that IDE drive and the drive will not be accessible even though it is actually running just fine.
This is where the Delay IDE Initial BIOS feature comes in. It allows you to force the BIOS to delay the initialization of IDE devices for up to 15 seconds. The delay allows your IDE devices more time to spin up before the BIOS initializes them.
If you do not use old IDE drives and the BIOS has no problem initializing your IDE devices, it is recommended that you leave the delay at the default value of 0 for the shortest possible booting time. Most IDE devices manufactured in the last few years will have no problem spinning up in time for initialization.
But if one or more of your IDE devices fail to initialize during the boot up process, start with a delay of 1 second. If that doesn’t help, gradually increase the delay until all your IDE devices initialize properly during the boot up process.
First Boot Device
Common Options : Floppy, LS/ZIP, HDD-0, SCSI, CDROM, HDD-1, HDD-2, HDD-3, LAN, Disabled
Quick Review
This BIOS feature allows you to select the first device from which the BIOS will attempt to load an operating system. If the BIOS finds and loads an operating system from the device selected through this feature, it won’t load another operating system, even if you have one on a different device.
By default, Floppy is the first boot device in practically all motherboards. But, unless you boot often from the floppy drive, it is better to set your hard disk (usually HDD-0) as the first boot device. This will shorten the booting process because the BIOS no longer needs to check the floppy drive for a bootable operating system.
To install operating systems that come on bootable CD-ROMs (i.e. Microsoft Windows XP) in a new hard disk, you will need to select CDROM as the first boot device. This enables you to boot directly from the CD-ROM and load the operating system’s installation routine.
Init Display First
Common Options : AGP, PCI
Quick Review
This BIOS feature allows you to select whether to boot the system using the AGP graphics card or the PCI graphics card. This is particularly important if you have AGP and PCI graphics cards but only one monitor.
If you are only using a single graphics card, then the BIOS will detect it as such and boot it up, irrespective of what you set the feature to. However, there may be a slight reduction in the time taken to detect and initialize the card if you select the proper setting for this BIOS feature. For example, if you only use an AGP graphics card, then setting Init Display First to AGP may speed up your system’s booting-up process.
Therefore, if you are only using a single graphics card, it is recommended that you set the Init Display First feature to the proper setting for your system (AGP for a single AGP card and PCI for a single PCI card).
But if you are using multiple graphics cards, it is up to you which card you want to use as your primary display card. It is recommended that you select the fastest graphics card as the primary display card.

Primary Graphics Adapter
Common Options : AGP, PCI
Details
Quick Review
This BIOS feature allows you to select whether to boot the system using the AGP graphics card or the PCI graphics card. This is particularly important if you have AGP and PCI graphics cards but only one monitor.
If you are only using a single graphics card, then the BIOS will detect it as such and boot it up, irrespective of what you set the feature to. However, there may be a slight reduction in the time taken to detect and initialize the card if you select the proper setting for this BIOS feature. For example, if you only use an AGP graphics card, then setting Primary Graphics Adapter to AGP may speed up your system’s booting-up process.
Therefore, if you are only using a single graphics card, it is recommended that you set the Primary Graphics Adapter feature to the proper setting for your system (AGP for a single AGP card and PCI for a single PCI card).
But if you are using multiple graphics cards, it is up to you which card you want to use as your primary display card. It is recommended that you select the fastest graphics card as the primary display card.
Primary VGA BIOS
Common Options : AGP VGA Card, PCI VGA Card
Quick Review
This BIOS feature allows you to select whether to boot the system using the AGP graphics card or the PCI graphics card. This is particularly important if you have AGP and PCI graphics cards but only one monitor.
If you are only using a single graphics card, then the BIOS will detect it as such and boot it up, irrespective of what you set the feature to. However, there may be a slight reduction in the time taken to detect and initialize the card if you select the proper setting for this BIOS feature. For example, if you only use an AGP graphics card, then setting Primary VGA BIOS to AGP VGA Card may speed up your system’s booting-up process.
Therefore, if you are only using a single graphics card, it is recommended that you set the Primary VGA BIOS feature to the proper setting for your system (AGP VGA Card for a single AGP card and PCI VGA Card for a single PCI card).
But if you are using multiple graphics cards, it is up to you which card you want to use as your primary display card. It is recommended that you select the fastest graphics card as the primary display card.
Quick Boot
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to decrease the time it takes to boot up the computer by shortening or skipping certain standard booting procedures.
If enabled, the BIOS will shorten the booting process by skipping some tests and shortening others. In addition, it will also perform the following tricks to further speed up the booting process :-
 Spin up the hard disks as soon as power is supplied (or as soon as possible)
 Initialize only critical parts of the chipset
 Read memory size from the SPD (Serial Presence Detect) chip on the memory modules
 Eliminate logo delays (inserted by many manufacturers)
If disabled, the BIOS will run the whole gamut of boot-up tests.
It is recommended that you disable this feature when you boot up a new computer for the first time or whenever you install a new piece of hardware. This allows the BIOS to run full diagnostic tests to detect any problems that may slip past Quick Boot’s abbreviated testing scheme.
After a few error-free test runs, you should enable this feature for much faster booting.
Quick Power On Self Test
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to decrease the time it takes to boot up the computer by shortening or skipping certain standard booting procedures.
If enabled, the BIOS will shorten the booting process by skipping some tests and shortening others.
If disabled, the BIOS will run the whole gamut of boot-up tests.
It is recommended that you disable this feature when you boot up a new computer for the first time or whenever you install a new piece of hardware. This allows the BIOS to run full diagnostic tests to detect any problems that may slip past the abbreviated testing scheme.
After a few error-free test runs, you should enable this feature for much faster booting.
Report No FDD For Win95
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to set if the BIOS should report the absence of a floppy disk drive to Windows 95.
For some reason, the Microsoft Windows 95 operating system requires a floppy disk drive to be present. However, in an age of USB flash media and CD/DVD writers, not all computers come with a floppy disk drive. Such computers will fail to boot up Windows 95 without a floppy disk drive.
If this feature is enabled, the BIOS will assign IRQ 6 to another device. This allows computers with no floppy disk drives to boot into Windows 95 normally.
If this feature is disabled, Windows 95 will detect the absence of the floppy disk drive and halt the system with an error message.
If you are using Windows 95 without a floppy disk drive, you have to enable this feature to allow Windows 95 to boot up normally.
If you are using Windows 95 with a floppy disk drive, you can enable or disable this feature. Windows 95 will boot up normally either way.
Please note that this BIOS feature has no relevance in other operating systems. Only Windows 95 is affected. It does not matter what you set this BIOS option to if you are using other operating systems.
Reset Configuration Data
Common Options : Enabled, Disabled
Quick Review
If you install a new piece of hardware or modify your computer’s hardware configuration, the BIOS will automatically detect the changes and reconfigure the ESCD (Extended System Configuration Data). Therefore, there is usually no need to manually force the BIOS to reconfigure the ESCD.
However, the occasion may arise where the BIOS may not be able to detect the hardware changes. A serious resource conflict may occur and the operating system may not even boot as a result. This is where the Reset Configuration Data BIOS feature comes in.
This BIOS feature allows you to manually force the BIOS to clear the previously saved ESCD data and reconfigure the settings. All you need to do is enable this BIOS feature and then reboot your computer. The new ESCD should resolve the conflict and allow the operating system to load normally.
Please note that the BIOS will automatically reset it to the default setting of Disabled after reconfiguring the new ESCD. So, there is no need for you to manually disable this feature after rebooting.
Resource Controlled By
Common Options : Auto, Manual
Quick Review
This BIOS feature determines if the BIOS should automatically configure IRQ and DMA resources.
The BIOS is generally capable of automatically configuring IRQ and DMA resources for the devices in your computer. Therefore, it is advisable that you set this feature to Auto.
However, if the BIOS has problems assigning the resources properly, you can select the Manual option to reveal the IRQ and DMA assignment fields. You can then assign each IRQ or DMA channel to either Legacy ISA or PCI/ISA PnP devices.
Legacy ISA devices are compliant with the original PC AT bus specification and require a specific interrupt and/or DMA channel to function properly. PCI/ISA PnP devices, on the other hand, adhere to the Plug and Play standard and can use any interrupt or DMA channel.
Second Boot Device
Common Options : Floppy, LS/ZIP, HDD-0, SCSI, CDROM, HDD-1, HDD-2, HDD-3, LAN, Disabled
Quick Review
This BIOS feature allows you to select the second device from which the BIOS will attempt to load an operating system. If the BIOS finds and loads an operating system from the device selected through this feature, it won’t load another operating system, even if you have one on a different device.
By default, HDD-0 is the second boot device in practically all motherboards. But, unless you boot often from the floppy drive (which is often the first boot device), it is better to set your hard disk (HDD-0) as the first boot device. This will shorten the boot process because the BIOS no longer needs to check the floppy drive for a bootable operating system.
More importantly, doing so prevents the BIOS from loading the wrong operating system in case you forgot to remove the boot disk from the floppy drive! This also indirectly prevents the loading of any virus-infected floppy disk that was left in the drive during booting.

Third Boot Device
Common Options : Floppy, LS/ZIP, HDD-0, SCSI, CDROM, HDD-1, HDD-2, HDD-3, LAN, Disabled
Quick Review
This BIOS feature allows you to select the third device from which the BIOS will attempt to load an operating system. If the BIOS finds and loads an operating system from the device selected through this feature, it won’t load another operating system, even if you have one on a different device.
By default, LS/ZIP is the third boot device in practically all motherboards. As the third boot device is only tried after no bootable operating system can be found in the first two boot devices, it is of little consequence what you set here. Therefore, the choice of boot device for this BIOS feature is entirely up to your personal preference.
Graphics Subsystem

AGP 2X Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is a toggle for the motherboard’s AGP 2X support.
When enabled, it allows the AGP bus to make use of the AGP 2X transfer protocol to boost the AGP bus bandwidth. If it’s disabled, then the AGP bus will only use the standard AGP1X transfer protocol.
The AGP 2X protocol must be supported by both the motherboard and graphics card for this feature to work. Of course, this feature will only appear in your BIOS if your motherboard supports the AGP 2X transfer protocol!
So, all you need to do is make sure your graphics card supports AGP 2X transfers. If it does, enable AGP 2X Mode to take advantage of the faster transfer mode. Disable it only if you are facing stability issues or if you intend to overclock the AGP bus beyond 75MHz with sidebanding support enabled.
AGP 4X Drive Strength
Common Options : Auto, Manual
Quick Review
This BIOS feature allows you to set whether the AGP controller should dynamically adjust the AGP driving strength or allow manual configuration by the BIOS.
Normally it is recommended that you set this feature to Auto. The AGP drive strength values will be provided by the auto-compensation circuitry. However, manual configuration of the AGP drive strength may be necessary to get certain AGP 4X cards to work properly.
To correct such compatibility problems, you should set the AGP 4X Drive Strength to Manual. This allows you to manually set a higher AGP Drive Strength value via the AGP Drive Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this feature is a little different from AGP Driving Control because it usually comes with two to four different drive strength controls. The AGP Driving Control feature only comes with a single drive strength control.
AGP 4X Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is a toggle for the motherboard’s AGP 4X support.
When enabled, it allows the AGP bus to make use of the AGP 4X transfer protocol to boost the AGP bus bandwidth. If it’s disabled, then the AGP bus will only use the AGP 1X or AGP 2X transfer protocol.
The AGP 4X protocol must be supported by both the motherboard and graphics card for this feature to work. Of course, this feature will only appear in your BIOS if your motherboard supports the AGP 4X transfer protocol!
So, all you need to do is make sure your graphics card supports AGP 4X transfers. If it does, enable AGP 4X Mode to take advantage of the faster transfer mode. You must disable it if your graphics card doesn’t support AGP 4X transfers. The BIOS will then report that the maximum supported transfer mode is AGP 2X.
AGP 8X Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is a toggle for the motherboard’s AGP 8X support.
When enabled, it allows the AGP bus to make use of the AGP 8X transfer protocol to boost the AGP bus bandwidth. If it’s disabled, then the AGP bus is only allowed to use the AGP 4X transfer protocol.
The AGP 8X protocol must be supported by both the motherboard and graphics card for this feature to work. Of course, this feature will only appear in your BIOS if your motherboard supports the AGP 8X transfer protocol!
So, all you need to do is make sure your graphics card supports AGP 8X transfers. If it does, enable AGP 8X Mode to take advantage of the faster transfer mode. You must disable it if your graphics card doesn’t support AGP 8X transfers. The BIOS will then report that the maximum supported transfer mode is AGP 4X.
AGP Always Compensate
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines if the AGP controller should be allowed to dynamically adjust the AGP driving strength or use preset drive strength values.
By default, it is set to automatically adjust the AGP drive strength once or at regular intervals. The circuitry can also be disabled or bypassed and a user setting used. However, this BIOS feature does not allow manual configuration.
When you enable AGP Always Compensate, the auto-compensation circuitry will automatically adjust the AGP drive strength at regular intervals. If you disable it, the circuitry will only adjust the drive strength once at boot-up. The drive strength values derived at boot-up will remain until the system is rebooted.
It is recommended that you enable AGP Always Compensate so that the AGP controller can dynamically adjust the AGP driving strength at regular intervals.
AGP Aperture Size
Common Options : 4, 8, 16, 32, 64, 128, 256
Quick Review
This BIOS feature does two things. It selects the size of the AGP aperture and it determines the size of the GART (Graphics Address Relocation Table).
The aperture is a portion of the PCI memory address range that is dedicated for use as AGP memory address space while the GART is a translation table that translates AGP memory addresses into actual memory addresses which are often fragmented. The GART allows the graphics card to see the memory region available to it as a contiguous piece of memory range.
Host cycles that hit the aperture range are forwarded to the AGP bus without need for translation. The aperture size also determines the maximum amount of system memory that can be allocated to the AGP graphics card for texture storage.
Please note that the AGP aperture is merely address space, not actual physical memory in use. Although it is very common to hear people recommending that the AGP aperture size should be half the size of system memory, that is wrong!
The requirement for AGP memory space shrinks as the graphics card’s local memory increases in size. This is because the graphics card will have more local memory to dedicate to texture storage. So, if you upgrade to a graphics card with more memory, you shouldn’t be “deceived” into thinking that you will need even more AGP memory! On the contrary, a smaller AGP memory space will be required.
It is recommended that you keep the AGP aperture around 64MB to 128MB in size, even if your graphics card has a lot of onboard memory. This allows flexibility in the event that you actually need extra memory for texture storage. It will also keep the GART (Graphics Address Relocation Table) within a reasonable size.
AGP Clock / CPU FSB Clock
Common Options : 1/1, 2/3, 1/2, 2/5
Quick Review
This BIOS feature allows you to set the ratio between the AGP clock speed and the CPU bus (also know as front side bus or FSB) clock speed. This allows you to keep the AGP bus speed within specifications (66MHz) while using a much faster CPU bus speed.
When the ratio is set to 1/1, the AGP bus will run at the same speed as the CPU bus. This is meant for processors that use the 66MHz bus speed, like the older Intel Celeron processors.
The 2/3 divider is used when you use a processor running with a bus speed of 100MHz. This divider will cut the AGP bus speed down to 66MHz.
The 1/2 divider is used when you use a processor running with a bus speed of 133MHz. This divider will cut the AGP bus speed down to 66MHz.
The 2/5 divider is used when you use a processor running with a bus speed of 166MHz. This divider will cut the AGP bus speed down to 66MHz.
Generally, you should set this feature according to the CPU bus speed you are using. This means using the 1/1 divider for 66MHz bus speed CPUs, the 2/3 divider for 100MHz bus speed CPUs, the 1/2 divider for 133MHz CPUs and the 2/5 divider for 166MHz CPUs.
AGP Drive Strength
Common Options : Auto, Manual
Quick Review
This BIOS feature allows you to set whether the AGP controller should dynamically adjust the AGP driving strength or allow manual configuration by the BIOS.
Normally it is recommended that you set this feature to Auto. The AGP drive strength values will be provided by the auto-compensation circuitry. However, manual configuration of the AGP drive strength may be necessary to get certain AGP 4X/8X cards to work properly.
To correct such compatibility problems, you should set the AGP Drive Strength to Manual. This allows you to manually set a higher AGP Drive Strength value via the AGP Drive Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this feature is a little different from AGP Driving Control because it usually comes with two to four different drive strength controls. The AGP Driving Control feature only comes with a single drive strength control.
AGP Drive Strength N Ctrl
Common Options : 0 to F (Hex numbers), 0h to Fh
Quick Review
This BIOS feature will only be activated if you set the AGP Drive Strength BIOS feature to Manual. It determines the N transistor drive strength of the AGP bus.
The drive strength is represented by Hex values from 0 to F (0 to 15 in decimal). The higher the drive strength, the greater the compensation for the motherboard’s impedance on the AGP bus.
In conjunction with AGP Drive Strength and AGP Drive Strength P Ctrl, this function is used to bypass AGP dynamic compensation in cases where the auto-compensation circuitry cannot provide adequate compensation. Please check with your graphics card manufacturer if your card requires the N transistor drive strength to be manually set.
Incidentally, increasing the AGP drive strength will not improve the performance of the AGP bus. It is not a performance enhancing feature so you shouldn’t increase the N transistor drive strength unless you need to.
AGP Drive Strength P Ctrl
Common Options : 0 to F (Hex numbers), 0h to Fh
Quick Review
This BIOS feature will only be activated if you set the AGP Drive Strength BIOS feature to Manual. It determines the P transistor drive strength of the AGP bus.
The drive strength is represented by Hex values from 0 to F (0 to 15 in decimal). The higher the drive strength, the greater the compensation for the motherboard’s impedance on the AGP bus.
In conjunction with AGP Drive Strength and AGP Drive Strength N Ctrl, this function is used to bypass AGP dynamic compensation in cases where the auto-compensation circuitry cannot provide adequate compensation. Please check with your graphics card manufacturer if your card requires the P transistor drive strength to be manually set.
Incidentally, increasing the AGP drive strength will not improve the performance of the AGP bus. It is not a performance enhancing feature so you shouldn’t increase the P transistor drive strength unless you need to.
AGP Driving Control
Common Options : Auto, Manual
Quick Review
This BIOS feature allows you to set whether the AGP controller should dynamically adjust the AGP driving strength or allow manual configuration by the BIOS.
Normally it is recommended that you set this feature to Auto. The AGP drive strength values will be provided by the auto-compensation circuitry. However, manual configuration of the AGP drive strength may be necessary to get certain AGP 4X/8X cards to work properly.
To correct such compatibility problems, you should set the AGP Drive Strength to Manual. This allows you to manually set a higher AGP Drive Strength value via the AGP Driving Value function.
Please note that this feature is a little different from AGP 4X Drive Strength because it usually comes with a single drive strength control. The AGP 4X Drive Strength feature comes with two to four drive strength controls.
AGP Driving Value
Common Options : 00 to FF (Hex numbers), 00h to FFh
Quick Review
This BIOS feature will only be activated if you set the AGP Driving Control BIOS feature to Manual. It determines the overall drive strength of the AGP bus.
The drive strength is represented by Hex values from 00 to FF (0 to 255 in decimal). The higher the drive strength, the greater the compensation for the motherboard’s impedance on the AGP bus.
In conjunction with AGP Drive Strength and AGP Drive Strength P Ctrl, this function is used to bypass AGP dynamic compensation in cases where the auto-compensation circuitry cannot provide adequate compensation. If you are using an AGP card built around the NVIDIA GeForce 2 line of GPUs, then it is recommended that you put AGP Driving Control into Manual mode and set AGP Driving Value to EA (234). For other cards, please check with the manufacturer if your card requires the AGP driving strength to be manually set.
Incidentally, increasing the AGP drive strength will not improve the performance of the AGP bus. It is not a performance enhancing feature so you shouldn’t increase the AGP drive strength unless you need to.

AGP Fast Write
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the AGP bus’ Fast Write capability. Fast Write is a feature which accelerates memory write transactions from the chipset to the AGP device.
Fast Write allows the AGP device act like a PCI device. This allows it to bypass the main memory and directly access the data which improves AGP read performance. However AGP write performance is not affected.
It is recommended that you enable AGP Fast Write for better AGP read performance but disable it if any of your PCI cards start acting funny.
AGP ISA Aliasing
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to determine if the system controller will perform ISA aliasing to prevent conflicts between ISA devices.
The default setting of Enabled forces the system controller to alias ISA addresses using address bits [15:10]. This restricts all 16-bit addressing devices to a maximum contiguous I/O space of 256 bytes.
When disabled, the system controller will not perform any ISA aliasing and all 16 address lines can be used for I/O address space decoding. This gives 16-bit addressing devices access to the full 64KB I/O space.
It is recommended that you disable AGP ISA Aliasing for optimal AGP (and PCI) performance. It will also prevent your AGP or PCI cards from conflicting with your ISA cards. Enable it only if you have ISA devices that are conflicting with each other.
AGP Master 1WS Read
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to reduce the time the AGP bus-mastering device has to wait before it can initiate a read command, to only one wait state. This speeds up all reads that the AGP bus-master makes from the system memory.
So, for better AGP read performance, enable this feature. Disable it only if you notice visual anomalies or if your system hangs on running software that make use of AGP texturing.
Curiously, some motherboards apparently come with a default AGP master read latency of 0! Enabling the AGP Master 1WS Read in such cases will actually increase the latency by one wait state and reduce AGP read performance. Although it’s quite unlikely that the default AGP master read latency would be zero, that’s what their manuals say.
AGP Master 1WS Write
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to reduce the time the AGP bus-mastering device has to wait before it can initiate a write command, to only one wait state. This speeds up all writes that the AGP bus-master makes to the system memory.
So, for better AGP read performance, enable this feature. Disable it only if you notice visual anomalies or if your system hangs on running software that make use of AGP texturing.
Curiously, some motherboards apparently come with a default AGP master write latency of 0! Enabling the AGP Master 1WS Write in such cases will actually increase the latency by one wait state and reduce AGP write performance. Although it’s quite unlikely that the default AGP master write latency would be zero, that’s what their manuals say.
AGP Prefetch
Common Options : Enabled, Disabled
Quick Review
This feature controls the system controller’s AGP prefetch capability.
When enabled, the system controller will prefetch data whenever the AGP device reads from the system memory. This speeds up AGP reads as it allows contiguous memory reads by the AGP device to proceed with minimal delay.
Therefore, it is recommended that you enable this feature for better AGP read performance.
AGP Secondary Lat Timer
Common Options : 00h, 20h, 40h, 60h, 80h, C0h, FFh
Quick Review
This BIOS feature controls how long the AGP bus can hold the PCI bus (via the PCI-to-PCI bridge) before another PCI device takes over. The longer the latency, the longer the AGP bus can retain control of the PCI bus before handing it over to another PCI device.
Normally, the AGP Secondary Latency Timer is set to 20h (32 clock cycles). This means the AGP bus’ PCI-to-PCI bridge has to complete its transactions within 32 clock cycles or hand it over to the next PCI device.
For better AGP performance, a longer latency should be used. Try increasing it to 40h (64 cycles) or even 80h (128 cycles). The optimal value for every system is different. You should benchmark your AGP card’s performance after each change to determine the optimal latency for your system.
If you set the AGP Secondary Latency Timer to a very large value like 80h (128 cycles) or C0h (192 cycles), it is recommended that you set the PCI Latency Time to 32 cycles. This provides better access for your PCI devices that might be unnecessarily stalled if both the AGP and PCI buses have very long latencies.
In addition, some time-critical PCI devices may not agree with a long AGP latency. Such devices require priority access to the PCI bus which may not be possible if the PCI bus is held up by the AGP bus for a long period. In such cases, it is recommended that you keep to the default latency of 20h (32 clock cycles).
AGP Spread Spectrum
Common Options : 0.25%, 0.5%, Disabled
Quick Review
This BIOS feature allows you to reduce the EMI of the AGP bus by modulating the signals it generates so that the spikes are reduced to flatter curves. It achieves this by varying the frequency slightly so that the signal does not use any particular frequency for more than a moment.
The BIOS usually offers two levels of modulation – 0.25% or 0.5%. The greater the modulation, the greater the reduction of EMI. Therefore, if you need to significantly reduce the AGP bus’ EMI, a modulation of 0.5% is recommended.
In most conditions, frequency modulation via this feature should not cause any problems. However, system stability may be compromised if you are overclocking the AGP bus. Of course, this depends on the amount of modulation, the extent of overclocking and other factors like temperature, etc. As such, the problem may not readily manifest itself immediately.
Therefore, it is recommended that you disable this feature if you are overclocking the AGP bus. The risk of crashing your system is not worth the reduction in EMI. Of course, if EMI reduction is important to you, enable this feature by all means. But you should reduce the clock speed a little to provide a margin of safety.
If you are not overclocking, the decision to enable or disable this feature is really up to you. But unless you have EMI problems or sensitive data that must be safeguarded from electronic eavesdropping, it is best to disable this feature to remove the possibility of stability issues.

AGP to DRAM Prefetch
Common Options : Enabled, Disabled
Quick Review
This feature controls the system controller’s AGP prefetch capability.
When enabled, the system controller will prefetch data whenever the AGP device reads from the system memory. This speeds up AGP reads as it allows contiguous memory reads by the AGP device to proceed with minimal delay.
Therefore, it is recommended that you enable this feature for better AGP read performance.
AGPCLK / CPUCLK
Common Options : 1/1, 2/3, 1/2, 2/5
Quick Review
This BIOS feature allows you to set the ratio between the AGP clock speed and the CPU bus (also know as front side bus or FSB) clock speed. This allows you to keep the AGP bus speed within specifications (66MHz) while using a much faster CPU bus speed.
When the ratio is set to 1/1, the AGP bus will run at the same speed as the CPU bus. This is meant for processors that use the 66MHz bus speed, like the older Intel Celeron processors.
The 2/3 divider is used when you use a processor running with a bus speed of 100MHz. This divider will cut the AGP bus speed down to 66MHz.
The 2/5 divider is used when you use a processor running with a bus speed of 166MHz. This divider will cut the AGP bus speed down to 66MHz.
Generally, you should set this feature according to the CPU bus speed you are using. This means using the 1/1 divider for 66MHz bus speed CPUs, the 2/3 divider for 100MHz bus speed CPUs, the 1/2 divider for 133MHz CPUs and the 2/5 divider for 166MHz CPUs.
DBI Output for AGP Trans.
Common Options : Enabled, Disabled
Quick Review
The full name for this BIOS feature is Dynamic Bus Inversion Output for AGP Transmitter. It is an AGP 3.0-specific BIOS feature which will only appear when you install an AGP 3.0-compliant graphics card.
When enabled, the AGP controller is allowed to use the Dynamic Bus Inversion scheme to reduce power consumption and signal noise.
When disabled, the AGP controller will not use the Dynamic Bus Inversion scheme to reduce power consumption and signal noise.
The AGP bus has 32 data lines divided into two sets. Sometimes, a large number of these data lines may switch together to the same polarity (either 1 or 0) and then switch back to the opposite polarity. This mass switching to the same polarity is called simultaneous switching outputs and it creates a lot of unwanted electrical noise at the AGP controller and GPU interfaces.
To avoid this, the AGP 3.0 specifications introduced a scheme called Dynamic Bus Inversion or DBI. It makes use of two new DBI lines – one for each 16-line set. These DBI lines are only supported by AGP 3.0-compliant graphics cards.
Dynamic Bus Inversion ensures that the data lines are limited to a maximum of 8 simultaneous switchings or transitions per 16-line set. It does so by switching the DBI line instead of the data lines when the number of simultaneous transitions exceeds 8 or 50% of the data lines. This ensures that electrical noise due to simultaneous switching outputs are minimized.
In short, DBI improves stability of the AGP interface by reducing signal noises that occur as a result of simultaneous switching outputs. It also reduces the AGP controller’s power consumption.
Therefore, it is recommended that you enable DBI Output for AGP Trans. to save power as well as reduce signal noise from simultaneous switching outputs.
Graphic Win Size
Common Options : 4, 8, 16, 32, 64, 128, 256
Quick Review
This BIOS feature does two things. It selects the size of the AGP aperture (hence, the name Graphic Windows Size) and it determines the size of the GART (Graphics Address Relocation Table).
The aperture is a portion of the PCI memory address range that is dedicated for use as AGP memory address space while the GART is a translation table that translates AGP memory addresses into actual memory addresses which are often fragmented. The GART allows the graphics card to see the memory region available to it as a contiguous piece of memory range.
Host cycles that hit the aperture range are forwarded to the AGP bus without need for translation. The aperture size also determines the maximum amount of system memory that can be allocated to the AGP graphics card for texture storage.
Please note that the AGP aperture is merely address space, not actual physical memory in use. Although it is very common to hear people recommending that the AGP aperture size should be half the size of system memory, that is wrong!
The requirement for AGP memory space shrinks as the graphics card’s local memory increases in size. This is because the graphics card will have more local memory to dedicate to texture storage. So, if you upgrade to a graphics card with more memory, you shouldn’t be “deceived” into thinking that you will need even more AGP memory! On the contrary, a smaller AGP memory space will be required.
It is recommended that you keep the AGP aperture around 64MB to 128MB in size, even if your graphics card has a lot of onboard memory. This allows flexibility in the event that you actually need extra memory for texture storage. It will also keep the GART (Graphics Address Relocation Table) within a reasonable size.
No Mask of SBA FE
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the masking of the signal used to calibrate the SBA (Sideband Address) port. It is used to fix compatibility issues with certain graphics cards.
When enabled, the chipset will mask (hide) the SBA calibration signal so that the graphics chip will not initiate the SBA calibration cycle. Since the SBA port is never recalibrated, the issue of graphics card hanging due to SBA recalibration is avoided.
When disabled, the graphics chip is allowed to initiate the SBA calibration cycle right after the AGP bus calibration cycle.
Users of ATI R300-based graphics cards (i.e. Radeon 9700 Pro, Radeon 9800) are advised to enable this BIOS feature if the graphic card hangs or crashes during 3D benchmarking or gaming.
Users of other unaffected graphics cards are advised to disable this feature so that the chipset can dynamically calibrate the SBA port.
PCI/VGA Palette Snoop
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines if your graphics card should allow VGA palette snooping by a fixed function display card. It is only useful if you use a fixed-function display card that requires a VGA-compatible graphics card to be present (i.e. MPEG decoder card).
Such fixed-function display cards generally do not have their own VGA palette. So, they have to “snoop” VGA palette data from the graphics card to generate the proper colours. Normally, the graphics card’s Feature Connector is used for this purpose.
When this feature is enabled, the graphics card will not respond to framebuffer writes. It will forward them to the fixed-function display card via its Feature Connector. The fixed-function display card will then snoop the palette data and generate the proper colours.
When this feature is disabled, the graphics card will display all framebuffer writes.
It is recommended that you disable this feature if you do not use any fixed-function display card like a MPEG decoder card.
But if you are using a fixed-function display card that requires palette snooping, enable this feature. Otherwise, the colours displayed may not be accurate and the monitor will blank out once you stop using the fixed-function display card.
Post Write Combine
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to control the USWC (Uncached Speculative Write Combining) write combine buffers.
If enabled, the write combine buffers will accumulate and combine partial or smaller graphics writes from the processor and write them to the graphics card as burst writes.
If disabled, the write combine buffers will be disabled. All graphics writes from the processor will be written to the graphics card directly.
It is highly recommended that you enable this feature for improved graphics and processor performance.
However, if you are using an older graphics card, it may not be compatible with this feature. Enabling this feature with such graphics cards will cause a host of problems like graphics artifacts, system crashes and even the inability to boot up properly.
If you face such problems, you should disable this BIOS feature immediately.
USWC Write Posting
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to control the USWC (Uncached Speculative Write Combining) write combine buffers.
If enabled, the write combine buffers will accumulate and combine partial or smaller graphics writes from the processor and write them to the graphics card as burst writes.
If disabled, the write combine buffers will be disabled. All graphics writes from the processor will be written to the graphics card directly.
It is highly recommended that you enable this feature for improved graphics and processor performance.
However, if you are using an older graphics card, it may not be compatible with this feature. Enabling this feature with such graphics cards will cause a host of problems like graphics artifacts, system crashes and even the inability to boot up properly.
If you face such problems, you should disable this BIOS feature immediately.
Video BIOS Cacheable
Common Options : Enabled, Disabled
Quick Review
This BIOS feature aims to further boost the performance of a shadowed video BIOS by caching it using the processor’s Level 2 cache. It works in conjunction with Video BIOS Shadowing and is only valid when Video BIOS Shadowing feature is enabled.
If this BIOS feature is enabled, a 32KB block of the video BIOS from C0000h-C7FFFh will be cached by the processor’s Level 2 cache. This greatly speeds up subsequent consecutive accesses to the video BIOS.
If this BIOS feature is disabled, the video BIOS will not be cached. The video BIOS will be read from the system memory (if it has been shadowed) or directly from the BIOS chip.
However, caching the video BIOS does not necessarily translate into better system performance. First of all, modern operating systems like Microsoft Windows XP do not need to use the video BIOS. They bypass the BIOS completely and use the graphics card’s driver instead. Therefore, absolutely no benefit can be realized by caching the BIOS.
And unlike system memory which can be a gigabyte or more, the processor’s L2 cache is a limited resource. Diverting such a large portion of the L2 cache for the purpose of caching the video BIOS will deprive the processor of L2 cache for its own data. Consequently, there will be a significant deterioration in processor performance whenever the video BIOS is cached.
As with the Video BIOS Shadowing feature, Flash ROM upgrades should not be attempted if the video BIOS is cached. If the video BIOS is cached, any attempt at flashing the video BIOS will likely result in a system crash. Worse of all, since only 32KB of the video BIOS is cached, the end result is usually a corrupted video BIOS.
Of course, caching the video BIOS will theoretically provide a significant boost in real-mode DOS games or certain operating systems in fail-safe mode. However, the loss of the processor’s L2 cache will negate any performance advantage gained by caching the video BIOS.
Therefore, it is recommended that you disable Video BIOS Caching, even if you play a lot of real-mode DOS games or work with operating systems running in fail-safe mode.
Video BIOS Shadowing
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows faster access to the video BIOS by shadowing or making a copy of it in the system memory. This appears quite an attractive feature since it results in at least a thousand-fold improvement in video BIOS performance and the only price you pay is losing the small amount of system memory used to mirror the video BIOS. Unfortunately, the truth is not so simple.
Modern operating systems do not even use the video BIOS. They bypass the BIOS completely and use the graphics card’s driver instead. Therefore, absolutely no benefit can be realized by shadowing the BIOS.
In addition, shadowing the video BIOS can sometimes cause conflicts to occur. There is always a risk of certain software writing to the RAM region used to shadow the video BIOS. When this happens, a conflict occurs and the system will crash.
What could be a bigger issue would be the shadowing of just a portion of the video BIOS. Newer video BIOSes are generally much larger than 32KB in size. But most motherboards shadow only a 32KB block from C0000 to C7FFF. If only this region of the video BIOS is shadowed and the rest left unshadowed, applications may have trouble accessing the video BIOS properly.
Finally, all graphics cards now use Flash ROM which allows easy upgrading of the firmware by a simple BIOS flash. However, if the video BIOS is shadowed, any attempt at flashing the video BIOS will likely result in a system crash. It could be even worse if only a portion of the video BIOS had been shadowed when the video BIOS upgrade was attempted.
With all that said, there may still be a use or two for this BIOS feature. For one thing, most real-mode DOS games use the video BIOS’s VGA functions because they cannot directly access the graphics processor. Such games will benefit from the shadowing of the video BIOS.
Shadowing of the video BIOS also provides performance benefits when it comes to the fail-safe mode of certain operating systems (for example, Safe Mode in Microsoft Windows XP). These operating systems fall back on the video BIOS because all video BIOSes contain the same, standardized VGA functions.
If this BIOS feature is enabled, the video BIOS will be shadowed in system memory. This improves graphics rendering performance if the VGA functions of the video BIOS are used.
If this BIOS feature is disabled, the video BIOS will not be shadowed in system memory. Any access to the video BIOS will have to go through the XT or LPC bus.
Since drivers have replaced the video BIOS as the interface between the graphics hardware and the operating system, it is recommended that you disable Video BIOS Shadowing. The risk of crashes and BIOS corruptions due to this BIOS feature is not worth the benefits it provides in certain circumstances.
However, if you do play a lot of old real-mode DOS games or work a lot in safe-mode Windows, then you should shadow the video BIOS for improved performance.
Video Memory Cache Mode
Common Options : USWC, UC
Quick Review
This is yet another BIOS feature with a misleading name. It does not cache the video memory or even graphics data (such data is uncacheable anyway).
This BIOS feature allows you to control the USWC (Uncached Speculative Write Combining) write combine buffers.
If enabled, the write combine buffers will accumulate and combine partial or smaller graphics writes from the processor and write them to the graphics card as burst writes.
If disabled, the write combine buffers will be disabled. All graphics writes from the processor will be written to the graphics card directly.
It is highly recommended that you enable this feature for improved graphics and processor performance.
However, if you are using an older graphics card, it may not be compatible with this feature. Enabling this feature with such graphics cards will cause a host of problems like graphics artifacts, system crashes and even the inability to boot up properly.
If you face such problems, you should disable this BIOS feature immediately.
Video RAM Cacheable
Common Options : Enabled, Disabled
Quick Review
This BIOS feature aims to boost VGA graphics performance by using the processor’s Level 2 cache to cache the 64KB VGA graphics memory area from A0000h to AFFFFh.
If this BIOS feature is enabled, the VGA graphics memory area will be cached by the processor’s Level 2 cache. This speeds up accesses to the VGA graphics memory area.
If this BIOS feature is disabled, the VGA graphics memory area will not be cached by the processor’s Level 2 cache.
From what we have discussed so far, it sounds like caching the VGA graphics memory area is logically the way to go. Caching the VGA graphics memory area will definitely speed up VGA graphics performance by caching accesses to the graphics memory area.
However, reality is far less ideal. For one thing, VGA modes are hardly used at all these days. For compatibility reason, VGA is still used in Windows XP’s Safe Mode. It is also used in real mode DOS, if you still use that. Other than that, there is no more use for VGA modes. If VGA graphics modes are not used, no benefit can possibly be realized by enabling this BIOS feature.
Even if you use DOS modes a lot, is there even a point in caching the VGA graphics memory area for better performance? Even the slowest computer today is more than capable of handling VGA graphics with ease. In short, caching the VGA graphics memory area will not bring any noticeable advantage.
On the other hand, caching this memory area will cost you some processor performance. Because some of the processor’s Level 2 cache is being diverted to cache the VGA graphics memory area, there is less to keep the processor supplied with data. Consequently, the processor’s performance suffers.
Therefore, it is highly recommended that you disable this BIOS feature. There is no reason to enable it even if you use real mode DOS a lot or work a lot in Windows Safe Mode.
Memory Subsystem

Act Bank A to B CMD Delay
Common Options : 2 Cycles, 3 Cycles
Quick Review
This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges.
For desktop PCs, a delay of 2 cycles is recommended as current surges aren’t really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device’s read and write performance.
Switch to 3 cycles only when there are stability problems with the 2 cycles setting.

Delay DRAM Read Latch
Common Options : Auto, No Delay, 0.5ns, 1.0ns, 1.5ns
Quick Review
This feature is similar to the DRAM Read Latch Delay BIOS feature. It fine-tunes the DRAM timing parameters to adjust for different DRAM loadings.
The DRAM load changes with the number as well as the type of memory modules installed. DRAM loading increases as the number of memory modules increases. It also increases if you use double-sided modules instead of single-sided ones. In short, the more DRAM devices you use, the greater the DRAM loading.
With heavier DRAM loads, you may need to delay the moment when the memory controller latches onto the DRAM device during reads. Otherwise, the memory controller may fail to latch properly onto the desired DRAM device and read from it.
The Auto option allows the BIOS to select the optimal amount of delay from values preset by the manufacturer.
The No Delay option forces the memory controller to latch onto the DRAM device without delay, even if the BIOS presets indicate that a delay is required.
The three timing options (0.5ns, 1.0ns and 1.5ns) give you manual control of the read latch delay.
Normally, you should let the BIOS select the optimal amount of delay from values preset by the manufacturer (using the Auto option). But if you notice that your system has become unstable upon installation of additional memory modules, you should try setting the DRAM read latch delay yourself.
The amount of delay should just be enough to allow the memory controller to latch onto the DRAM device in your particular situation. Don’t unnecessarily increase the delay. Start with 0.5ns and work your way up until your system stabilizes.
If you have a light DRAM load, you can ensure optimal performance by manually using the No Delay option. If your system becomes unstable after using the No Delay option, simply revert back to the default value of Auto so that the BIOS can adjust the read latch delay to suit the DRAM load.
DRAM Act to PreChrg CMD
Common Options : 5T, 6T, 7T, 8T, 9T
Quick Review
Like SDRAM Tras Timing Value, this BIOS feature controls the memory bank’s minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated. Hence, the name DRAM Act to PreChrg CMD which is short for DRAM Activate Command to Precharge Command.
If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.
But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable.
DRAM Data Integrity Mode
Common Options : ECC, Non-ECC
Quick Review
This BIOS feature controls the ECC feature of the memory controller.
ECC, which stands for Error Checking and Correction, enables the memory controller to detect and correct single-bit soft memory errors. The memory controller will also be able to detect double-bit errors although it will not be able to correct them. This provides increased data integrity and system stability. However, this feature can only be enabled if you are using special ECC memory modules.
Because present day processors use 64-bit wide data paths, 72-bit (64-bit data + 8-bit ECC) ECC memory modules are required to implement ECC. Please note that the maximum data transfer rate of the 72-bit ECC memory module is the same as the 64-bit memory module. The extra 8-bits are only for the ECC code and do not carry any data. So, using 72-bit memory modules will not give you any boost in performance.
In fact, because the memory controller has to calculate the ECC code for every data word that is read or written, there will be some performance degradation, roughly in the region of 3-5%. This is one of the reasons why ECC memory modules are not popular among desktop users. Throw in the fact that ECC memory modules are both expensive and hard to come by; and you have the top three reasons why ECC memory modules will never be mainstream solutions.
If you are using standard 64-bit memory modules, you must select the Non-ECC option.
But if you have already forked out the money for 72-bit ECC memory modules, you should enable the ECC feature, no matter what people say about losing some memory performance. It doesn’t make sense to buy expensive ECC memory modules and then disable ECC! Remember, you are not really losing performance. You are just trading it for greater stability and data integrity.
DRAM Idle Timer
Common Options : 0T, 8T, 16T, 64T, Infinite, Auto
Quick Review
This BIOS feature sets the number of idle cycles that is allowed before the memory controller forces such open pages to close and precharge.
The premise behind this BIOS feature is the concept of temporal locality. According to this concept, the longer the open page is left idle, the less likely it will be accessed again before it needs to be precharged. Therefore, it would be better to prematurely close and precharge the page so that it can be opened quickly when a data request comes along.
It can be set to a variety of clock cycles from 0T to 64T. This sets the number of clock cycles the open pages are allowed to idle before they are closed and precharged. There’s also an Infinite option as well as an Auto option.
If you select 0 Cycle, then the memory controller will immediately precharge the open pages as soon as there’s an idle cycle.
If you select Infinite, the memory controller will never precharge the open pages prematurely. The open pages will be left activated until they have to be precharged.
If you select Auto, the memory controller will use the manufacturer’s preset default setting.
Most manufacturers use a default value of 8T which allows the memory controller to precharge the open pages once eight idle cycles have passed.
For general desktop use, it is recommended that you choose the Infinite option so that precharging can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.
For applications (i.e. servers) that perform a lot of random accesses, it is advisable that you select 0T as subsequent data requests would most likely be fulfilled by other pages. Closing open pages to precharge will prepare those pages for the next data request that hits them. There’s also the added benefit of increased data integrity due to more frequent refreshes.
DRAM Interleave Time
Common Options : 0ms, 0.5ms
Quick Review
This BIOS feature determines the amount of additional delay between successive bank accesses when the SDRAM Bank Interleave feature has been enabled. Naturally, the shorter the delay, the faster the memory module can switch between banks and consequently perform better.
Therefore, it is recommended that you set the DRAM Interleave Time as low as possible for better memory performance. In this case, it would be 0ms which introduces no additional delay between bank accesses. Increase the DRAM Interleave Time to 0.5ms only if you experience instability with the 0ms setting.
DRAM PreChrg to Act CMD
Common Options : 2T, 3T, 4T
Quick Review
Like SDRAM Trp Timing Value, this BIOS feature controls the RAS precharge time (tRP). This constitutes the time it takes for the Precharge command to complete and the row to be available for activation. Hence, the name DRAM PreChrg to Act CMD, which is short for DRAM Precharge Command to Activate Command.
If the RAS precharge time is too long, it will reduce performance by delaying all row activations. Reducing the precharge time to 2T improves performance by allowing a new row to be activated earlier.
However, the short precharge time of 2T may be insufficient for some memory modules. In such cases, the active row may lose its contents before they can be returned to the memory bank and the row deactivated. This may cause data loss or corruption when the memory controller attempts to read from the active row or write to it.
Therefore, it is recommended that you reduce the RAS precharge time to 2T for better performance but increase it to 3T or 4T if you experience system stability issues after reducing the precharge time.
DRAM Ratio (CPU:DRAM)
Common Options : 1:1, 3:2, 3:4, 4:5, 5:4
Quick Review
The choice of options in this BIOS feature depends entirely on the setting of the DRAM Ratio H/W Strap or N/B Strap CPU As BIOS feature.
When DRAM Ratio H/W Strap has been set to Low, the available options are 1:1 and 3:4.
When DRAM Ratio H/W Strap has been set to High, the available options are 1:1 and 4:5.
When N/B Strap CPU As has been set to PSB800, the available options are 1:1, 3.2 and 5:4.
When N/B Strap CPU As has been set to PSB533, the available options are 1:1 and 4:5.
When N/B Strap CPU As has been set to PSB400, the only available option is 3:4.
The options of 1:1, 3:2, 3:4 and 4:5 refer to the available CPU-to-DRAM (or CPU:DRAM) ratios.
Please note that while the Pentium 4 processor is said to have a 400MHz or 533MHz or 800MHz FSB (front side bus), the front side bus (also known as CPU bus) is actually only running at 100MHz or 133MHz or 200MHz respectively. This is because the Pentium 4 bus is a Quad Data Rate or QDR bus which transfers four times as much data as a single data rate bus.
For marketing reasons, the Pentium 4 bus is labeled as running at 400MHz or 533MHz or 800MHz when it is actually running at only 100MHz, 133MHz and 200MHz respectively. It is important to keep this in mind when setting this BIOS feature.
For example, if you set a 3:2 ratio with a 200MHz (800MHz QDR) CPU bus, the memory bus will run at (200MHz / 3) x 2 = 133MHz or 266MHz DDR.
By default, this BIOS feature is set to By SPD. This allows the chipset to query the SPD (Serial Presence Detect) chip on every memory module and use the appropriate ratio.
It is recommended that you select the ratio that allows you to maximize your memory modules’ capabilities. But bear in mind that synchronous operation using the 1:1 ratio is also highly desirable as it allows a high throughput.
DRAM Ratio H/W Strap
Common Options : High, Low, By CPU
Quick Review
This BIOS feature allows you to circumvent the CPU-to-DRAM ratio limitation found in the newer Intel i845-series of chipsets. In those chipsets, Intel has chosen to limit the choices of available CPU-to-DRAM ratios.
When a 400MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1 or 3:4.
When a 533MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1 or 4:5.
Fortunately, this BIOS feature allows you to circumvent that limitation.
The DRAM Ratio H/W Strap BIOS feature actually controls the setting of the external hardware reset strap assigned to the MCH (Memory Controller Hub) of the chipset. By setting it High or Low, you can trick the chipset into thinking that the 400MHz FSB or the 533MHz FSB is being used.
When this BIOS feature is set to High, you will be able to access the 533MHz CPU-to-DRAM ratios of 1:1 and 4:5.
When this BIOS feature is set to Low, you will be able to access the 400MHz CPU-to-DRAM ratios of 1:1 and 3:4.
By default, this BIOS feature is set to By CPU, whereby the hardware strap will be set according to the actual FSB rating of the processor.
Generally, you do not need to manually adjust the hardware strap setting. But if you require access to the CPU-to-DRAM ratio that would normally not be available to you, then this BIOS feature would be very helpful indeed.
DRAM Read Latch Delay
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is similar to the Delay DRAM Read Latch BIOS feature. It fine-tunes the DRAM timing parameters to adjust for different DRAM loadings.
The DRAM load changes with the number as well as the type of memory modules installed. DRAM loading increases as the number of memory modules increases. It also increases if you use double-sided modules instead of single-sided ones. In short, the more DRAM devices you use, the greater the DRAM loading.
With heavier DRAM loads, you may need to delay the moment when the memory controller latches onto the DRAM device during reads. Otherwise, the memory controller may fail to latch properly onto the desired DRAM device and read from it.
The Auto option allows the BIOS to select the optimal amount of delay from values preset by the manufacturer.
The No Delay option forces the memory controller to latch onto the DRAM device without delay, even if the BIOS presets indicate that a delay is required.
The three timing options (0.5ns, 1.0ns and 1.5ns) give you manual control of the read latch delay.
Normally, you should let the BIOS select the optimal amount of delay from values preset by the manufacturer (using the Auto option). But if you notice that your system has become unstable upon installation of additional memory modules, you should try setting the DRAM read latch delay yourself.
The amount of delay should just be enough to allow the memory controller to latch onto the DRAM device in your particular situation. Don’t unnecessarily increase the delay. Start with 0.5ns and work your way up until your system stabilizes.
If you have a light DRAM load, you can ensure optimal performance by manually using the No Delay option. If your system becomes unstable after using the No Delay option, simply revert back to the default value of Auto so that the BIOS can adjust the read latch delay to suit the DRAM load.

DRAM Refresh Rate
Common Options : 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec, Auto
Quick Review
This BIOS feature allows you to set the refresh interval of the memory chips. There are three different settings as well as an Auto option. If the Auto option is selected, the BIOS will query the memory modules’ SPD chips and use the lowest setting found for maximum compatibility.
For better performance, you should consider increasing the DRAM Refresh Rate from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the DRAM Refresh Rate too much, the memory cells may lose their contents.
Therefore, you should start with small increases in the DRAM Refresh Rate and test your system after each hike before increasing it further. If you face stability problems upon increasing the refresh interval, reduce the refresh interval step by step until the system is stable.
Fast R-W Turn Around
Common Options : Enabled, Disabled
Quick Review
When the memory controller receives a write command immediately after a read command, an additional period of delay is normally introduced before the write command is actually initiated.
As its name suggests, this BIOS feature allows you to skip that delay. This improves the write performance of the memory subsystem. Therefore, it is recommended that you enable this feature for faster read-to-write turn-arounds.
However, not all memory modules can work with the tighter read-to-write turn-around. If your memory modules cannot handle the faster turn-around, the data that was written to the memory module may be lost or become corrupted. So, when you face stability issues, disable this feature to correct the problem.
Force 4-Way Interleave
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to force the memory controller to use the 4-bank SDRAM interleave mode which provides better performance than the 2-bank interleave mode. However, you must have at least 4 banks of memory in the system for this feature to work properly.
Normally, SDRAM modules that use 16Mbit memory chips (usually 32MB or smaller in size) have only two memory banks. So, if you are using such a small capacity DIMM, you should disable Force 4-Way Interleave. But if you use two or more of such DIMMs, you can still enable Force-4-Way Interleave.
SDRAM modules that use 64Mbit or larger memory chips are four-banked in nature. These modules are at least 64MB in size. If you are using such four-banked modules, it no longer matters if you are using just one module or several of them. You can enable Force 4-Way Interleave without fear.
Therefore, it is recommended that you enable this BIOS feature if you are using 64MB or larger memory modules or at least two 32MB or smaller memory modules. Otherwise, it is best to disable this BIOS feature.
For more information on memory bank interleaving, you should check out the details of the SDRAM Bank Interleave BIOS feature.
Gate A20 Option
Common Options : Normal, Fast
Quick Review
This BIOS feature is used to determine the method by which Gate A20 is controlled. The Normal option forces the chipset to use the slow keyboard controller to do the switching. The Fast option, on the other hand, allows the chipset to use its own 0x92 port for faster switching. No candy for guessing which is the recommended setting!
Please note this feature is only important for operating systems that switch a lot between real mode and protected mode. These operating systems include 16-bit operating systems like MS-DOS and 16-bit/32-bit hybrid operating systems like Microsoft Windows 98.
This feature has no effect if the operating system only runs in real mode (no operating system currently in use does that, as far as I know!) or if the operating system operates entirely in protected mode (i.e. Microsoft Windows XP). This is because if A20 mode switching is not required, then it does not matter at all if the switching was done by the slow keyboard controller or the faster 0x92 port.
With all that said and done, the recommended setting for this BIOS feature is still Fast, even with operating systems that don’t do much mode switching. Although using the 0x92 port to control Gate A20 has been known to cause spontaneous reboots in certain, very rare instances, there is really no reason why you should keep using the slow keyboard controller to turn A20 or or off.

MD Driving Strength
Common Options : Hi, Lo / High, Low
Quick Review
This BIOS feature offers simplified control of the memory data bus’ driving strength.
The default value is Lo or Low. With heavy DRAM loads, you might want to set this feature to Hi or High.
Due to the nature of this BIOS feature, it is possible to use it as an aid in overclocking the memory bus. Your memory module may not overclock as well as you want it to. By raising the driving strength of the memory bus, it is possible to improve its stability at overclocked speeds.
However, this is not a surefire way of overclocking the memory bus. All you may get at the end of the day is increased EMI and power consumption.
Please note too that increasing the memory bus drive strength will not improve the performance of your memory subsystem.
Therefore, it is recommended that you leave the MD Driving Strength at its default Lo or Low setting. Set it to Hi or High only if you have a heavy DRAM load or if you are trying to stabilize an overclocked memory module.
Memory Hole At 15M-16M
Common Options : Enabled, Disabled
Quick Review
Certain ISA cards require exclusive access to the 1MB block of memory, from the 15th to the 16th megabyte, to work properly. This BIOS feature allows you to reserve that 1MB block of memory for such cards to use.
If you enable this feature, 1MB of memory (the 15th MB) will be reserved exclusively for the ISA card’s use. This effectively reduces the total amount of memory available to the operating system by 1MB.
Please note that in certain motherboards, enabling this feature may actually render all memory above the 15th MB unavailable to the operating system!
If you disable this feature, the 15th MB of RAM will not be reserved for the ISA card’s use. The full range of memory is therefore available for the operating system to use. However, if your ISA card requires the use of that memory area, it may then fail to work.
Since ISA cards are a thing of the past, it is highly recommended that you disable this feature. Even if you have an ISA card that you absolutely have to use, you may not actually need to enable this feature.
Most ISA cards do not need exclusive access to this memory area. Make sure that your ISA card requires this memory area before enabling this feature. You should use this BIOS feature only in a last-ditch attempt to get a stubborn ISA card to work.
OS Select For DRAM > 64MB
Common Options : OS/2, Non-OS/2
Details
Quick Review
This BIOS feature determines how systems with more than 64MB of memory are managed. A wrong setting can cause problems like erroneous memory detection.
If you are using an older version of the IBM OS/2 operating system, you should select OS/2.
If you are using the IBM OS/2 Warp v3.0 or higher operating system, you should select Non-OS/2.
If you are using an older version of the IBM OS/2 operating system but have already installed all the relevant IBM FixPaks, you should select Non-OS/2.
Users of non-OS/2 operating systems (like Microsoft Windows XP) should select the Non-OS/2 option.
OS/2 Onboard Memory > 64M
Common Options : Enabled, Disabled
Quick Review
This is similar to the OS Select For DRAM > 64M BIOS feature.
This BIOS feature determines how systems with more than 64MB of memory are managed. A wrong setting can cause problems like erroneous memory detection.
If you are using an older version of the IBM OS/2 operating system, you should select Yes.
If you are using the IBM OS/2 Warp v3.0 or higher operating system, you should select No.
If you are using an older version of the IBM OS/2 operating system but have already installed all the relevant IBM FixPaks, you should select No.
Users of non-OS/2 operating systems (like Microsoft Windows XP) should select the No option.
Read-Around-Write
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows the processor to execute read commands out of order, as if they are independent from the write commands. It does this by using a Read-Around-Write buffer.
If this BIOS feature is enabled, all processor writes to memory are first accumulated in that buffer. This allows the processor to execute read commands without waiting for the write commands to be completed.
The buffer will then combine the writes and write them to memory as burst transfers. This reduces the number of writes to memory and boosts the processor’s write performance.
If this BIOS feature is disabled, the processor writes directly to the memory controller. This reduces the processor’s read performance.
Therefore, it is highly recommended that you enable this feature for better processor read and write performance.
Read Wait State
Common Options : 0 Cycle, 1 Cycle
Quick Review
This BIOS feature determines how long the memory controller should wait before sending read data to the data requester (i.e. processor, graphics card, etc..).
If this feature is set to 1 Cycle, the memory controller imposes a delay of one clock cycle before the data is sent to the requester. This reduces memory read performance since the memory controller delays the transfer of each piece of requested data by one clock cycle.
If this feature is set to 0 Cycle, the memory controller will transfer read data to the data requester without any delay.
Therefore, it is recommended that you set the Read Wait State to 0 Cycle for better memory read and write performance.
Please note that this may cause system instabilities in certain configurations. When that happens, just reset the value to 1 Cycle.

Refresh Interval
Common Options : 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec, Auto
Quick Review
This BIOS feature allows you to set the refresh interval of the memory chips. There are three different settings as well as an Auto option. If the Auto option is selected, the BIOS will query the memory modules’ SPD chips and use the lowest setting found for maximum compatibility.
For better performance, you should consider increasing the Refresh Interval from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Interval too much, the memory cells may lose their contents.
Therefore, you should start with small increases in the Refresh Interval and test your system after each hike before increasing it further. If you face stability problems upon increasing the refresh interval, reduce the refresh interval step by step until the system is stable.
Refresh Mode Select
Common Options : 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec, Auto
Quick Review
This BIOS feature allows you to set the refresh interval of the memory chips. There are three different settings as well as an Auto option. If the Auto option is selected, the BIOS will query the memory modules’ SPD chips and use the lowest setting found for maximum compatibility.
For better performance, you should consider increasing the Refresh Mode Select from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Mode Select too much, the memory cells may lose their contents.
Therefore, you should start with small increases in the Refresh Mode Select and test your system after each hike before increasing it further. If you face stability problems upon increasing the refresh interval, reduce the refresh interval step by step until the system is stable.

SDRAM 1T Command
Common Options : Enabled, Disabled, Auto
Quick Review
This BIOS feature allows you to select the delay between the assertion of the Chip Select signal till the time the memory controller starts sending commands to the memory bank. The lower the value, the sooner the memory controller can send commands out to the activated memory bank.
When this feature is enabled, the memory controller will only insert a command delay of only one clock cycle or 1T.
When this feature is enabled, the memory controller will insert a command delay of two clock cycles or 2T.
The Auto option allows the memory controller to use the memory module’s SPD value for command delay.
If the SDRAM command delay is too long, it can reduce performance by unnecessarily preventing the memory controller from issuing the commands sooner.
However, if the SDRAM command delay is too short, the memory controller may not be able to translate the addresses in time and the “bad commands” that result will cause data loss and corruption.
It is recommended that you try enabling SDRAM 1T Command for better memory performance. But if you face stability issues, disable this BIOS feature.
SDRAM 1T Command Control
Common Options : Enabled, Disabled, Auto
Quick Review
This BIOS feature allows you to select the delay between the assertion of the Chip Select signal till the time the memory controller starts sending commands to the memory bank. The lower the value, the sooner the memory controller can send commands out to the activated memory bank.
When this feature is enabled, the memory controller will only insert a command delay of only one clock cycle or 1T.
When this feature is enabled, the memory controller will insert a command delay of two clock cycles or 2T.
The Auto option allows the memory controller to use the memory module’s SPD value for command delay.
If the SDRAM command delay is too long, it can reduce performance by unnecessarily preventing the memory controller from issuing the commands sooner.
However, if the SDRAM command delay is too short, the memory controller may not be able to translate the addresses in time and the “bad commands” that result will cause data loss and corruption.
It is recommended that you try enabling SDRAM 1T Command Control for better memory performance. But if you face stability issues, disable this BIOS feature.
SDRAM Bank Interleave
Common Options : 2-Bank, 4-Bank, Disabled
Quick Review
This BIOS feature enables you to set the interleave mode of the SDRAM interface.
Interleaving allows banks of SDRAM to alternate their refresh and access cycles. One bank will undergo its refresh cycle while another is being accessed. This improves memory performance by masking the refresh cycles of each memory bank. A close examination will reveal that since the refresh cycles of all the memory banks are staggered, this produces a kind of pipelining effect.
However, bank interleaving only works if the addresses requested consecutively are not in the same bank. If they are in the same memory bank, then the data transactions behave as if the banks were not interleaved. The processor will have to wait until the first data transaction clears and that memory bank refreshes before it can send another address to that bank.
Each SDRAM module is internally divided into either two or four banks of memory. Double-banked SDRAM modules generally use 16Mbit SDRAM chips and are usually 32MB or smaller in size. Quad-banked SDRAM modules, on the other hand, usually use higher density (64Mbit-256Mbit) SDRAM chips. All SDRAM modules of at least 64MB in size are quad-banked in nature.
If you are using a single double-banked SDRAM module, set this feature to 2-Bank. This is the only option available for the single double-banked SDRAM module.
If you are using at least two double-banked SDRAM modules, you can use the 4-Bank option as well as the 2-Bank option. Of course, it is recommended that you select 4-Bank for better interleaving performance.
If you are using quad-banked SDRAM modules, you can use either interleave options. Of course, it is recommended that you select 4-Bank for better interleaving performance.
Because a 4-bank interleave always allows for better interleaving performance, it is highly recommended that you select the 4-Bank option if your system supports it. Use the 2-Bank option only if you are using a single double-banked SDRAM module.
Please note that Award (now part of Phoenix Technologies) recommends that SDRAM bank interleaving be disabled if 16Mbit SDRAM modules are used. This is because early 16Mbit SDRAM modules have stability problems with bank interleaving. The good news is all current SDRAM modules support bank interleaving.
SDRAM Burst Len
Common Options : 4, 8
Quick Review
This BIOS feature allows you to control the length of a burst transaction.
When this feature is set to 4, a burst transaction can only comprise of up to four reads or four writes.
When this feature is set to 8, a burst transaction can only comprise of up to eight reads or eight writes.
As the initial CAS latency is fixed for each burst transaction, a longer burst transaction will allow more data to be read or written for less delay than a shorter burst transaction. Therefore, a burst length of 8 will be faster than a burst length of 4.
Therefore, it is recommended that you select the longer burst length of 8 for better performance.
SDRAM Burst Length
Common Options : 4, 8
Quick Review
This BIOS feature allows you to control the length of a burst transaction.
When this feature is set to 4, a burst transaction can only comprise of up to four reads or four writes.
When this feature is set to 8, a burst transaction can only comprise of up to eight reads or eight writes.
As the initial CAS latency is fixed for each burst transaction, a longer burst transaction will allow more data to be read or written for less delay than a shorter burst transaction. Therefore, a burst length of 8 will be faster than a burst length of 4.
Therefore, it is recommended that you select the longer burst length of 8 for better performance.
SDRAM CAS Latency Time
Common Options : 2, 3 (SDR memory) or 1.5, 2, 2.5, 3 (DDR memory)
Quick Review
This BIOS feature controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur.
Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable.
Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.
SDRAM Command Rate
Common Options : 1T, 2T
Quick Review
This BIOS feature allows you to select the delay between the assertion of the Chip Select signal till the time the memory controller starts sending commands to the memory bank. The lower the value, the sooner the memory controller can send commands out to the activated memory bank.
If the SDRAM command delay is too long, it can reduce performance by unnecessarily preventing the memory controller from issuing the commands sooner.
However, if the SDRAM command delay is too short, the memory controller may not be able to translate the addresses in time and the “bad commands” that result will cause data loss and corruption.
It is recommended that you try the 1T command delay for better memory performance. But if you face stability issues, increase the command delay to 2T.
SDRAM Cycle Length
Common Options : 2, 3 (SDR memory) or 1.5, 2, 2.5, 3 (DDR memory)
Quick Review
This BIOS feature is same as the SDRAM CAS Latency Time BIOS feature. It controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur.
Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable.
Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.
SDRAM Cycle Time Tras/Trc
Common Options : 5/6, 6/8
Quick Review
This BIOS feature determines the tRAS and the tRC parameters of the SDRAM memory module.
tRAS refers to the SDRAM Row Active Time, which is the length of time the row will remain open for data transfers.
tRC, on the other hand, refers to the SDRAM Row Cycle Time, which determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row.
The default setting is 6/8 which is more stable and slower than 5/6. The 5/6 setting cycles faster but it may not leave the row open long enough for burst transactions to complete. When this happens, data may be lost and the contents of the memory cells may be corrupted.
For better memory performance, you should try the 5/6 setting. But increase it to 6/8 if your system becomes unstable.
SDRAM Idle Limit
Common Options : Disabled, 0 Cycle, 8 Cycles, 12 Cycles, 16 Cycles, 24 Cycles, 32 Cycles, 48 Cycles
Quick Review
This BIOS feature sets the number of idle cycles that is allowed before the memory controller forces such open pages to close and precharge.
The premise behind this BIOS feature is the concept of temporal locality. According to this concept, the longer the open page is left idle, the less likely it will be accessed again before it needs to be precharged. Therefore, it would be better to prematurely close and precharge the page so that it can be opened quickly when a data request comes along.
It can be set to a variety of clock cycles from 0 Cycle to 48 Cycles. This sets the number of clock cycles the open pages are allowed to idle before they are closed and precharged. There’s also a Disabled option.
If you select 0 Cycle, then the memory controller will immediately precharge the open pages as soon as there’s an idle cycle.
If you select Disabled, the memory controller will never precharge the open pages prematurely. The open pages will be left activated until they have to be precharged.
The default value is 8 cycles which allows the memory controller to precharge the open pages once eight idle cycles have passed.
For general desktop use, it is recommended that you disable this feature so that precharging can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.
For applications (i.e. servers) that perform a lot of random accesses, it is advisable that you select 0 Cycle as subsequent data requests would most likely be fulfilled by other pages. Closing open pages to precharge will prepare those pages for the next data request that hits them. There’s also the added benefit of increased data integrity due to more frequent refreshes.
SDRAM RAS Precharge Time
Common Options : 2, 3, 4
Quick Review
This BIOS feature sets the number of cycles required for the RAS to accumulate its charge before another row can be activated. If the RAS Precharge Time is too long, it will reduce performance by delaying all row activations. Reducing the precharge time to 2 improves performance by allowing a new row to be activated earlier.
However, the short precharge time of 2 may be insufficient for some memory modules. In such cases, the active row may lose its contents before they can be returned to the memory bank and the row deactivated. This may cause data loss or corruption when the memory controller attempts to read from the active row or write to it.
Therefore, it is recommended that you reduce the SDRAM RAS Precharge Time to 2 for better performance but increase it to 3 or 4 if you experience system stability issues after reducing the precharge time.
SDRAM RAS Pulse Width
Common Options : 4, 5, 6, 7, 8, 9
Quick Review
Like DRAM Act to PreChrg CMD, this BIOS feature controls the memory bank’s minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated.
If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.
But if you start getting memory errors or system crashes, increase the tRCD value one clock cycle at a time until your system becomes stable.
SDRAM RAS-to-CAS Delay
Common Options : 2, 3, 4
Quick Review
This BIOS feature allows you to set the delay between the RAS and CAS signals. The appropriate delay for your memory module is reflected in its rated timings. In JEDEC specifications, it is the second number in the three or four number sequence.
Because this delay occurs whenever the row is refreshed or a new row is activated, reducing the delay improves performance. Therefore, it is recommended that you reduce the delay to 3 or 2 for better memory performance.
Please note that if you use a value that is too low for your memory module, this can cause the system to be unstable. If your system becomes unstable after you reduce the RAS-to-CAS delay, you should increase the delay or reset it to the rated delay.
Interestingly, increasing the RAS-to-CAS delay may allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, you can try increasing the RAS-to-CAS delay.
SDRAM Row Active Time
Common Options : 4, 5, 6, 7, 8, 9
Quick Review
Like DRAM Act to PreChrg CMD, this BIOS feature controls the memory bank’s minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated.
If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.
But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable.
SDRAM Tras Timing Value
Common Options : 2, 3, 4, 5, 6, 7, 8, 9
Quick Review
This BIOS feature controls the memory bank’s minimum row active time (tRAS). This constitutes the length of time from the activate command to the precharge command of the same bank.
Now, tRAS is important because it determines how soon after a row activation can the same row be precharged for another cycle. If an exceedingly long tRAS is chosen, the row may be unnecessarily delayed from precharging for another cycle. But if you set it for too short a period, there may not be enough time to complete the read/write cycle. When that happens, data may be lost or corrupted.
For optimal performance, use the lowest value you can (usually 5 clock cycles). But if you start getting memory errors or system crashes, increase the value one clock cycle at a time until you get a stable system.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRP before selecting the tRAS value.
SDRAM Trp Timing Value
Common Options : 1, 2, 3, 4
Quick Review
This BIOS feature controls the memory bank’s precharge time (tRP). This constitutes the time it takes for the Precharge command to complete and the row to be available for activation.
Now, tRP is important because it determines how soon a row can be activated after a Precharge command has been issued. If an exceedingly long tRP is chosen, that may unnecessarily reduce performance by preventing the row from being activated earlier. But if you set it for too short a period, the row may not be sufficiently precharged and that may cause data loss or corruption when the memory controller attempts to read from that row.
For optimal performance, use the lowest value you can (usually 2 clock cycles). But if you start getting memory errors or system crashes, increase the value.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRAS before selecting the tRP value.
Super Bypass Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature basically allows the memory request organizer (MRO) of the memory controller to skip certain pipeline stages while transferring data to and from the memory subsystem.
This improves memory performance by allowing lower latency accesses to the memory subsystem. However, this feature can only be safely enabled if the following conditions are true :-
1. The system only has a single processor present. Systems using dual-processor motherboards can enable this feature if only one processor is present.
2. The processor clock speed multiplier must be 4 or greater. This means the processor must be running at least four times faster than its bus speed.
For better memory performance, it is recommended that you enable this feature. However, you must make sure that you are only using a single processor that is running at least four times faster than the processor bus. You should disable this feature if your system does not meet the two requirements stated above.
Super Bypass Wait State
Common Options : 0 Cycle, 1 Cycle
Quick Review
This BIOS feature is used to fine-tune the Super Bypass feature to correct for internal timing variations.
When set to 0 Cycle, the memory controller initiates all super bypass requests without delay.
When set to 1 Cycle, the memory controller forces a wait state delay for all super bypass requests.
Official documents recommend that a wait state be added for a 133MHz (266MHz DDR) memory bus. Systems using a 100MHz (200MHz DDR) memory bus do not need this delay.
Forcing a wait state on all super bypass requests reduces the effectiveness of the Super Bypass feature. Therefore, it is recommended that you try using the 0 Cycle setting for maximum performance.
However, if you experience system stability issues after using this 0 Cycle setting, set this feature to 1 Cycle. This slows down super bypass transactions but will allow your system to use the Super Bypass feature at higher clock speeds.
SuperStability Mode
Common Options : Enabled, Disabled
Quick Review
This is a NVIDIA nForce chipset-specific BIOS feature. It controls the hitherto hidden “feature” of the nForce chipset which locks the memory clock at 200MHz, instead of rated 266MHz; when it detects a memory module that is not compatible with the motherboard. This allows the use of substandard or incompatible memory modules, albeit at reduced performance.
The chipset will only allow the memory clock to be set at 266MHz when it is satisfied that each and every memory module installed has met its standard. If even a single module fails to meet the standard, the chipset will lock the memory clock at 200MHz, irrespective of the clock speed it was set to run at.
While NVIDIA claims that this feature allows nForce motherboards to work with substandard or incompatible memory modules that would otherwise be unusable, there have been reports that even compatible memory modules are being locked down to 200MHz. Apparently, loading the second slot (Slot B) of the second memory controller with a double-sided DIMM will also cause SuperStability to kick in.
After this feature was discovered by Chris Connolly of GamePC, the BIOS was revised to include this SuperStability Mode feature. This allows you to switch the SuperStability feature on or off.
When left at the default setting of Enabled, the nForce chipset will lock the memory clock at 200MHz if it detects an incompatible memory module or if Slot B of the second memory controller is filled with a double-sided memory module.
When disabled, the nForce chipset will not check the memory modules for incompatibility or Slot B of the second memory controller for a double-sided memory module. The memory modules will be allowed to run at the clock speed you set.
It is highly recommended that you disable SuperStability Mode for better SDRAM performance, especially if you use all three DIMM slots. There is really no need to enable it since you can lower the memory clock speed yourself or increase their timings in order to use incompatible memory modules.

Miscellaneous

Anti-Virus Protection
Common Options : Enabled, Disabled, ChipAway
Quick Review
This BIOS feature controls the motherboard’s virus protection features..
When enabled, the BIOS will protect the boot sector and partition table by halting the system and flashing a warning message whenever there’s an attempt to write to these areas.
This feature can cause problems with software that need to access the boot sector, i.e. the installation routine of all versions of Microsoft Windows from Windows 95 onwards. When enabled, this feature causes the installation routine to fail. You should disable this feature before running such software.
Alternatively, you can select the internal rule-based anti-virus code, i.e. ChipAway. Enabling ChipAway provides better anti-virus protection by scanning for and detecting boot viruses before they have a chance to infect the boot sector of any hard disk. But note that this feature is useless for hard disks that run on external controllers with their own BIOS.
Duplex Select
Common Options : Full-Duplex, Half-Duplex
Quick Review
This BIOS feature allows you to determine the transmission mode of the IR (Infra-Red) communications port.
Selecting Full-Duplex permits simultaneous two-way transmission, like a conversation over the phone.
Selecting Half-Duplex, on the other hand, only permits transmission in one direction at any one time, which is more like a conversation over the walkie-talkie.
Naturally, the Full-Duplex mode is the faster and more desirable choice. You should use Full-Duplex if possible.
Consult your IR peripheral’s manual to determine if it supports Full-Duplex transmission. The IR peripheral must support Full-Duplex for this option to work.

Flash BIOS Protection
Common Options : Enabled, Disabled
Quick Review
The Flash BIOS Protection feature is a software toggle that controls write access to the BIOS. When it is enabled, the BIOS code is write-protected and cannot be changed. This protects it from any attempt to modify it, including BIOS updates and virus attacks. Therefore, if you intend to update the BIOS, you’ll need to disable this feature first.
It is highly recommended that you enable this feature at all times. You should only disable it when you intend to update the BIOS. After updating the BIOS, you should immediately re-enable it to protect the BIOS against viruses.
Floppy 3 Mode Support
Common Options : Disabled, Drive A, Drive B, Both
Quick Review
For reasons best known to the Japanese, their computers come with special 3 mode 3.5″ floppy drives. While physically similar to the standard 3.5″ floppy drives used by the rest of the world, these 3 mode floppy drives differ in the disk formats they support.
Unlike normal floppy drives, 3 mode floppy drives support three different floppy disk formats – 1.44MB, 1.2MB and 720KB. Hence, their name. They allow the system to support the Japanese 1.2MB floppy disk format as well as the standard 1.44MB and 720KB (obsolete) disk formats.
If you own a 3 mode floppy drive and need to use the Japanese 1.2MB disk format, you must enable this feature by selecting either Drive A, Drive B or Both (if you have two 3 mode floppy drives). Otherwise, your 3 mode floppy drive won’t be able to read the special 1.2MB format properly.
However, if you only have a standard floppy drive, disable this feature or your floppy drive may not function properly.
Hardware Reset Protect
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is very useful for file servers and routers that need to be running 24 hours a day, 365 days a year. When it is enabled, the hardware reset button will be disabled. This prevents the possibility of any accidental resets. When disabled, the reset button will function as normal.
If you are running a mission-critical server or have kids who just love to press little red buttons, it is highly recommended that you enable this feature. Otherwise, it is really up to your preference. Naturally, people using buggy operating systems or applications are advised to keep this feature disabled for more convenient reboots. Heheh. 🙂
KBC Input Clock Select
Common Options : 8MHz, 12MHz, 16MHz
Quick Review
The PS/2 keyboard communicates with the keyboard controller on the motherboard via a serial data link. The speed of the data link depends on the clock signal generated by the keyboard controller. The higher the clock speed, the faster the keyboard interface. This translates into a more responsive keyboard although not all keyboards can work with higher clock speeds.
This BIOS feature allows you to adjust the keyboard interface clock for a better response or to fix a keyboard problem. It is recommended that you select the 16MHz option for a better keyboard response. But if the keyboard performs erratically or fails to initialize, try a lower clock speed.
Onboard IR Function
Common Options : IrDA (HPSIR) mode, ASK IR (Amplitude Shift Keyed IR) mode, Disabled
Quick Review
There are two different IR (Infra-Red) modes – IrDA and ASK IR.
You should select the IR mode that is supported by your external IR device. Choosing the wrong IR mode will prevent your computer from communicating with the external IR device.
But if there’s a choice between IrDA and ASK IR, the natural choice would be IrDA, of course! IrDA is faster and has a longer range.
Please note that such IR communications require an IR beam kit to be plugged into the IR header on the motherboard. Without the IR beam kit, this feature won’t have any effect.
You should also note that enabling this IR function prevents the second serial port from being used by normal serial devices. Therefore, if you do not need to use the onboard IR function, disable this BIOS feature so that the second serial port to be used by normal serial devices.
Onboard Parallel Port
Common Options : 3BCh/IRQ7, 278h/IRQ5, 378h/IRQ7, Disabled
Quick Review
This BIOS feature allows you to select the I/O address and IRQ for the onboard parallel port.
The default I/O address of 378h and IRQ of 7 should work well in most cases. Unless you have a problem with the parallel port, you should leave it at the default settings.
You should only select an alternative I/O address or IRQ if the default settings are causing a conflict with other devices.
You can also disable the onboard parallel port if you do not need to use it. Doing so frees up the I/O port and IRQ used by the parallel port. Those resources can then be reallocated for other devices to use.
Onboard Serial Port 1
Common Options : Auto, 3F8h/IRQ4, 2F8h/IRQ3, 3E8h/IRQ4, 2E8h/IRQ3, Disabled
Quick Review
This BIOS feature allows you to manually select the I/O address and IRQ for the first serial port.
It is recommended that you leave it as Auto so that the BIOS can select the best settings for it. But if you need a particular I/O port or IRQ that has been taken up by this serial port, you can manually select an alternative I/O port or IRQ for it.
Please note that any I/O port or IRQ can be used for the serial port. There is no advantage or disadvantage in any of the options. As long as you do not select an I/O port or IRQ that has already been allocated to another device, any option will do.
You can also disable this serial port if you do not need to use it. Doing so frees up the I/O port and IRQ used by this serial port. Those resources can then be reallocated for other devices to use.
Onboard Serial Port 2
Common Options : Auto, 3F8h/IRQ4, 2F8h/IRQ3, 3E8h/IRQ4, 2E8h/IRQ3, Disabled
Quick Review
This BIOS feature allows you to manually select the I/O address and IRQ for the first serial port.
It is recommended that you leave it as Auto so that the BIOS can select the best settings for it. But if you need a particular I/O port or IRQ that has been taken up by this serial port, you can manually select an alternative I/O port or IRQ for it.
Please note that any I/O port or IRQ can be used for the serial port. There is no advantage or disadvantage in any of the options. As long as you do not select an I/O port or IRQ that has already been allocated to another device, any option will do.
You can also disable this serial port if you do not need to use it. Doing so frees up the I/O port and IRQ used by this serial port. Those resources can then be reallocated for other devices to use.
Onboard USB Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature enables or disables the motherboard’s onboard USB controller.
It is recommend that you enable this feature so that you can use the onboard USB controller to communicate with your USB devices.
If you disable this feature, the USB controller will be disabled and you will not be able to use it to communicate with any USB device. This frees up an IRQ for other devices to use. This is useful when you have many devices that cannot share IRQs.
However, it is recommended that you do not disable this BIOS feature unless you do not use any USB device or if you are using a different USB controller for your USB needs.
Parallel Port Mode
Common Options : Normal (SPP), ECP, EPP, ECP+EPP
Quick Review
By default, the parallel port is usually set to the Normal (SPP) mode. SPP stands for Standard Parallel Port. It is the original transfer protocol for the parallel port. Therefore, it will work with all parallel port devices.
The ECP (Extended Capabilities Port) transfer mode uses the DMA protocol to achieve data transfer rates of up to 2MB/s and provides symmetric bidirectional communication.
On the other hand, EPP (Enhanced Parallel Port), now known as IEEE 1284, uses existing parallel port signals to provide asymmetric bidirectional communication. It was also designed for high-speed communications, offering transfer rates of up to 2MB/s.
As you can see, SPP is a very slow transfer mode. It should only be selected when faster transfer modes cannot be used (i.e. with old printers or scanners). With modern parallel port devices, the ECP and EPP modes are the transfer modes of choice.
Generally, because of its FIFOs and the DMA channel it uses, ECP is good at large data transfers. Therefore, it is the transfer mode that works best with scanners and printers. EPP is better with devices that switch between reads and writes frequently (like ZIP drives and hard disks).
However, you should check your parallel port device’s documentation before you set the transfer mode. The manufacturer of your parallel port peripheral may have designated a preferred transfer mode for the device in question. In that case, it is best to follow their recommendation.
If the device documentation did not state any preferred transfer mode and you still do not know what mode to select, you can select the ECP+EPP mode. If you select this mode, the BIOS will automatically determine the transfer mode to use for your device.
Power On Function
Common Options : Button Only, Keyboard 98, Hot Key, Mouse Left, Mouse Right
Quick Review
This BIOS feature allows you to select the method to turn on your computer.
By default, this feature is set to Button Only. This allows your computer to be started up only through the use of the power button or switch. Other available options :-
• A Keyboard 98-compatible keyboard (which comes with a wake-up button )
• A keyboard hot key (for non-Keyboard 98 keyboards)
• A mouse button (either the right or left button)
If you select the Mouse Left option, the left button of the mouse will be used to start up the system. The Mouse Right option selects the right mouse button as the power on button instead.
Please note that only PS/2 mice support the Mouse Left or Mouse Right options. Mice using serial or USB connections do not support this power on function.
The Keyboard 98 option will only work if you are using Windows 98 or better and have the appropriate keyboard. Then you can use the keyboard’s wake-up or power-on button to start up the computer.
Older keyboards that do not conform to the Keyboard 98 standard and therefore do not have the special wake-up button can use the Hot Key option instead. There are twelve hot keys available : Ctrl-F1 to Ctrl-F12. Select the hot key you want and you will be able to start up the computer using that hot key.
There is no performance advantage in choosing any one of the options above. So, choose the option that you are most comfortable with.
RxD, TxD Active
Common Options : Hi, Hi or Lo, Lo or Hi, Lo or Lo, Hi
Quick Review
This BIOS feature allows you to set the infra-red reception (RxD) and transmission (TxD) polarity.
It is usually found under the Onboard Serial Port 2 BIOS feature and is linked to the second serial port. So, if you disable that port, this feature will disappear from the screen or appear grayed out.
There are four options available, based on combinations of Hi and Lo. You’ll need to consult your IR peripheral’s documentation to determine the correct polarity. Choosing the wrong polarity will prevent a proper IR connection from being established with the IR peripheral.
Security Setup
Common Options : System, Setup
Quick Review
This BIOS feature controls the application of the BIOS’ password protection. It will only work once you have created a password through the Password Setting option in the main BIOS screen.
Selecting the System option will force the BIOS to ask for the password every time the system boots up.
If you choose Setup, then the password is only required for access to the BIOS. This option is useful for system administrators or computer resellers who need to keep novice users from messing around with the BIOS. 🙂
Spread Spectrum
Common Options : 0.25%, 0.5%, Smart Clock, Disabled
Quick Review
This BIOS feature allows you to reduce the EMI of your motherboard by modulating the signals it generates so that the spikes are reduced to flatter curves. It achieves this by varying the frequency slightly so that the signal does not use any particular frequency for more than a moment.
The BIOS usually offers two levels of modulation – 0.25% or 0.5%. The greater the modulation, the greater the reduction of EMI. Therefore, if you need to significantly reduce your motherboard’s EMI, a modulation of 0.5% is recommended.
In most conditions, frequency modulation via this feature should not cause any problems. However, system stability may be slightly compromised in certain situations. For example, this BIOS feature may cause improper functioning of timing-critical devices like clock-sensitive SCSI devices.
Spread Spectrum can also cause problems with overclocked systems, especially those that have been taken to extremes. Even a slight modulation of frequency may cause the processor or any other overclocked components of the system to fail, leading to very predictable consequences.
Therefore, it is recommended that you disable this feature if you are overclocking your system. The risk of crashing your system is not worth the reduction in EMI. Of course, if EMI reduction is important to you, enable this feature by all means. But you should reduce the clock speed a little to provide a margin of safety.
Some BIOSes also offer a Smart Clock option. Instead of modulating the frequency of signals over time, Smart Clock turns off the AGP, PCI and SDRAM clock signals that are not in use. Therefore, EMI can be reduced without compromising system stability. As a bonus, using Smart Clock also helps reduce power consumption. The degree of EMI and power reduction will depend on the number of empty AGP, PCI and SDRAM slots. But generally, Smart Clock won’t be able to reduce EMI as effectively as simple frequency modulation.
With that said, it is recommended that you enable Smart Clock, instead of the 0.25% or 5% option, if the option is available to you. It allows you to reduce some EMI without any risk of compromising your computer’s stability.
USB Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature enables or disables the motherboard’s onboard USB controller.
It is recommend that you enable this feature so that you can use the onboard USB controller to communicate with your USB devices.
If you disable this feature, the USB controller will be disabled and you will not be able to use it to communicate with any USB device. This frees up an IRQ for other devices to use. This is useful when you have many devices that cannot share IRQs.
However, it is recommended that you do not disable this BIOS feature unless you do not use any USB device or if you are using a different USB controller for your USB needs.
Virus Warning
Common Options : Enabled, Disabled
Quick Review
This BIOS feature provides rudimentary anti-virus protection by monitoring writes to the boot sector and partition table.
If this feature is enabled, the BIOS will halt the system and flash a warning message whenever it detects an attempt to write to the boot sector or the partition table.
If this feature is disabled, the BIOS will not monitor writes to the boot sector and partition table.
This feature can cause problems with software that need to access the boot sector. One good example is the installation routine of all versions of Microsoft Windows from Windows 95 onwards. When enabled, this feature causes the installation routine to fail. You should disable this feature before running such software.
Processor

Athlon 4 SSED Instruction
Common Options : Enabled, Disabled
Quick Review
Beginning with the Palomino core of the Athlon XP (and MP) family of processors, AMD started implementing Intel’s SSE instruction set. AMD also added a status bit which tells any querying software that the Athlon XP/MP supports the full SSE instruction set. However, this status bit ends up causing some compatibility issues with the BeOS operating system and some graphics cards.
This is where the Athlon 4 SSED Instruction BIOS feature comes in. This BIOS feature is a simple toggle for the AMD Athlon XP/MP’s SSE status bit.
When enabled, the BIOS will enable the SSE status bit. Querying software will recognize the processor as a SSE-compatible processor. This allows the processor to take advantage of SSE-optimized software.
When disabled, the BIOS will disable the SSE status bit. Querying software will not recognize the processor as a SSE-compatible processor. The processor can only take advantage of Enhanced 3DNow!-optimized software.
By default, this BIOS feature is set to Enabled, which allows for optimal performance with SSE-optimized software. It is highly recommended that you leave it at the default setting of Enabled.
You should disable this BIOS feature only if you are facing compatibility issues with the SSE status bit.
Auto Turn Off PCI Clock Pin
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the BIOS should actively reduce EMI (Electromagnetic Interference) and reduce power consumption by turning off unoccupied or inactive PCI slots.
When enabled, the BIOS will monitor PCI slots and turn off clock signals to all unoccupied and inactive slots.
When disabled, the BIOS will not monitor PCI slots. All clock signals will remain active even to unoccupied or inactive slots.
It is recommended that you enable this feature to save power and reduce EMI.
Clock Throttle
Common Options : 12.5%, 25.0%, 37.5%, 50.0%, 62.5%, 75.0%, 87.5%
Quick Review
This BIOS feature determines the clock speed of the processor when it is in the Suspend To RAM (STR) power saving mode. It has no effect when the processor is in normal active mode.
Available options for this BIOS feature are set values of the processor’s power consumption. They range from a low of 12.5% to a high of 87.5%. Please note that these options reflect the desired power consumption of the processor, not its clock speed. The clock speed of the processor will be determined based on the option chosen.
The default setting is usually 62.5%. This means the processor will be running at a clock speed that allows it to use 37.5% less power.
The choice of what you should set the processor to run at is really up to you. The lower the value, the more power you will save when the processor is in Suspend To RAM mode. Generally, it would be nice to minimize power consumption while in Suspend To RAM mode. The only potential drawback might be a slightly longer time required to bring the processor back to speed.
It is common for this BIOS feature to be mistaken as a BIOS control for the Pentium 4’s Thermal Monitor feature. However, the clock throttling provided by this BIOS feature is completely different from the Pentium 4’s Thermal Monitor feature.
Compatible FPU OPCODE
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines how Pentium 4 and Xeon processors handle FOP codes using the FOP (final opcode) register.
When enabled, the Pentium 4 and Xeon will engage the FOP code compatibility mode, which stores the FOP of the last non-transparent instruction in the FOP register.
When disabled, the Pentium 4 and Xeon will turn off the FOP code compatibility mode and store only the FOP of the last non-transparent floating point instruction that had an unmasked exception. This allows for better FPU performance.
Therefore, it is recommended that you disable this feature for better FPU performance unless your software requires this feature to recover from FPU exceptions.

CPU Drive Strength
Common Options : 0, 1, 2, 3
Quick Review
This BIOS feature allows you to manually set the drive strength of the CPU bus. The higher the value, the stronger the drive strength.
If you are facing stability problems with your processor, you might want to try boosting the CPU drive strength to a higher value. It will help to correct any possible increase in impedance from the motherboard. Due to the nature of this BIOS feature, it is also possible to use it as an aid in overclocking the CPU.
However, this is not a surefire way of overclocking the CPU. Increasing it to the highest value will not necessarily mean that you can overclock the CPU more than you already can. In addition, it is important to note that increasing the CPU drive strength will not improve its performance. Contrary to popular opinion, it is not a performance-enhancing feature.
CPU Fast String
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the processor’s fast string feature.
When enabled, the processor will operate on the string in a cache line when the “fast string” conditions are met.
When disabled, the processor will not operate on the string while it is in a cache line.
It is recommended that you enable CPU Fast String for better performance. There is currently no reason why you should disable CPU Fast String.
CPU Hyper-Threading
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the Intel Hyper-Threading Technology.
The Intel Hyper-Threading Technology allows a single processor to execute two or more separate threads concurrently. When hyper-threading is enabled, multi-threaded software applications can execute their threads in parallel, thereby improving their performance.
The Intel Hyper-Threading Technology is only supported by the Intel Pentium 4 (officially only those 3.06GHz and faster) and the Intel Xeon processors. Please note that for Hyper-Threading to work, you should have the following :-
– an Intel processor that supports Hyper-Threading
– a motherboard with a chipset and BIOS that support Hyper-Threading
– an operating system which supports Hyper-Threading (Microsoft Windows XP or Linux 2.4.x)
Since it behaves like two separate processors with their own APICs, you should also enable APIC Function in the BIOS, which is required for multi-processing.
It is highly recommended that you enable CPU Hyper-Threading for improved processor performance.
CPU L2 Cache ECC Checking
Common Options : Enabled, Disabled
Quick Review
This BIOS feature enables or disables the L2 (Level 2 or Secondary) cache’s ECC (Error Checking and Correction) function, if available.
Enabling this feature is recommended because it will detect and correct single-bit errors in data stored in the L2 cache. As most data reads are satisfied by the L2 cache, the L2 cache’s ECC function should catch and correct almost all single-bit errors in the memory subsystem.
It will also detect double-bit errors although it cannot correct them. But this isn’t such a big deal since double-bit errors are extremely rare. For all practical purposes, the ECC check should be able to catch virtually all data errors. This is especially useful at overclocked speeds when errors are most likely to creep in.
So, for most intents and purposes, I recommend that you enable this feature for greater system stability and reliability.
Please note that the presence of this feature in the BIOS does not necessarily mean that your processor’s L2 cache actually supports ECC checking. Many processors do not ship with ECC-capable L2 cache. In such cases, you can still enable this feature in the BIOS but it will have no effect.
CPU Level 1 Cache
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the processor’s Level 1 cache.
When enabled, the processor’s Level 1 cache will be allowed to function. This allows the best possible performance from the processor.
When disabled, the processor’s Level 1 cache will be disabled. The processor will bypass the Level 1 cache and rely only on the Level 2 and Level 3 (if available) caches. This reduces the performance of the processor.
The recommended setting is obviously Enabled since disabling it severely affects the processor’s performance. However, the Disabled setting is useful as a troubleshooting tool, especially when you are overclocking your processor.
CPU Level 2 Cache
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the processor’s Level 2 cache.
When enabled, the processor’s Level 2 cache will be allowed to function. This allows the best possible performance from the processor.
When disabled, the processor’s Level 2 cache will be disabled. The processor will bypass the Level 2 cache and rely only on the Level 1 and Level 3 (if available) caches. This reduces the performance of the processor.
The recommended setting is obviously Enabled since disabling it severely affects the processor’s performance. However, the Disabled setting is useful as a troubleshooting tool, especially when you are overclocking your processor.
CPU Level 3 Cache
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the processor’s Level 3 cache.
When enabled, the processor’s Level 3 cache will be allowed to function. This allows the best possible performance from the processor.
When disabled, the processor’s Level 3 cache will be disabled. The processor will bypass the Level 3 cache and rely only on the Level 1 and Level 2 caches. This reduces the performance of the processor.
The recommended setting is obviously Enabled since disabling it severely affects the processor’s performance. However, the Disabled setting is useful as a troubleshooting tool, especially when you are overclocking your processor.
CPU Thermal-Throttling
Common Options : 12.5%, 25.0%, 37.5%, 50.0%, 62.5%, 75.0%, 87.5%
Quick Review
This BIOS feature determines the clock speed of the processor when it is in the Suspend To RAM (STR) power saving mode. It has no effect when the processor is in normal active mode.
Available options for this BIOS feature are set values of the processor’s power consumption. They range from a low of 12.5% to a high of 87.5%. Please note that these options reflect the desired power consumption of the processor, not its clock speed. The clock speed of the processor will be determined based on the option chosen.
The default setting is usually 62.5%. This means the processor will be running at a clock speed that allows it to use 37.5% less power.
The choice of what you should set the processor to run at is really up to you. The lower the value, the more power you will save when the processor is in Suspend To RAM mode. Generally, it would be nice to minimize power consumption while in Suspend To RAM mode. The only potential drawback might be a slightly longer time required to bring the processor back to speed.
It is common for this BIOS feature to be mistaken as a BIOS control for the Pentium 4’s Thermal Monitor feature. However, the clock throttling provided by this BIOS feature is completely different from the Pentium 4’s Thermal Monitor feature.
CPU VCore Voltage
Common Options : Std. Vcore, Raising
Quick Review
This is a BIOS feature so far seen only in the ABIT NV7-series of motherboards. It is used to give a small boost to the processor’s core voltage.
When set to Std. Vcore, the motherboard will supply the processor with the default core voltage.
When set to Raising, the motherboard will boost the processor’s core voltage by approximately 3%. So, if your processor has a core voltage of 1.7 volts, using the Raising option raises that voltage to about 1.75V.
As you can see, the voltage boost courtesy of this BIOS feature is not remarkable. But since it appears to be the only way to boost the processor’s core voltage in NVIDIA nForce-based motherboards, this 3% boost is better than nothing at all! It may not allow radical overclocking but it should allow a little more overclocking freedom.
If you are an overclocker, it is recommended that you select the Raising option. It should allow your processor to be a little more overclockable. At the very least, it will improve its stability at overclocked speeds.
Delay Prior To Thermal
Common Options : 4 Minutes, 8 Minutes, 16 Minutes, 32 Minutes
Quick Review
This BIOS feature is only valid for systems that are powered by 0.13µ Intel Pentium 4 processors with 512KB L2 cache. These processors come with a Thermal Monitor which actually consists of a on-die thermal sensor and a Thermal Control Circuit (TCC).
When the Thermal Monitor is in automatic mode and the thermal sensor detects that the processor has reached its maximum safe operating temperature, it will activate the TCC. The TCC will then modulate the clock cycles by inserting null cycles, typically at a rate of 50-70% of the total number of clock cycles. This results in the processor “resting” 50-70% of the time.
As the die temperature drops, the TCC will gradually reduce the number of null cycles until no more is required to keep the die temperature below the safe point. Then the thermal sensor turns the TCC off. This mechanism allows the processor to dynamically adjust its duty cycles to ensure its die temperature remains within safe limits.
The Delay Prior To Thermal BIOS feature controls the activation of the Thermal Monitor’s automatic mode. It allows you to determine when the Pentium 4’s Thermal Monitor should be activated in automatic mode after the system boots. For example, with the default value of 16 Minutes, the BIOS activates the Thermal Monitor in automatic mode 16 minutes after the system starts booting up.
Generally, the Thermal Monitor should not be activated immediately on booting as the processor will be under a heavy load during the booting process. This causes a sharp rise in die temperature from its cold state. Because it takes time for the thermal output to radiate from the die to the heat sink, the thermal sensor will register the sudden spike in die temperature and prematurely activate the TCC. This unnecessarily reduces the processor’s performance during the booting up process.
Therefore, to ensure optimal booting performance, the activation of the Thermal Monitor must be delayed for a set period of time.
It is recommended that you set this BIOS feature to the lowest value (in minutes) that exceeds the time it takes to fully boot up your computer. For example, if it takes 5 minutes to fully boot up your system, you should select 8 Minutes.
You should not select a delay value that is unnecessarily long. Without the Thermal Monitor, your processor may heat up to a critical temperature (approximately 135°C), at which point the thermal sensor shuts down your processor by removing the core voltage within 0.5 seconds.

FPU OPCODE Compatible Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines how Pentium 4 and Xeon processors handle FOP codes using the FOP (final opcode) register.
When enabled, the Pentium 4 and Xeon will engage the FOP code compatibility mode, which stores the FOP of the last non-transparent instruction in the FOP register.
When disabled, the Pentium 4 and Xeon will turn off the FOP code compatibility mode and store only the FOP of the last non-transparent floating point instruction that had an unmasked exception. This allows for better FPU performance.
Therefore, it is recommended that you disable this feature for better FPU performance unless your software requires this feature to recover from FPU exceptions.
Host Bus In-Order Queue Depth
Common Options : 1, 4, 8, 12
Quick Review
This BIOS feature controls the use of the processor bus’ command queue. Normally, there are only two options available. Depending on the motherboard chipset, the options could be (1 and 4), (1 and 8) or (1 and 12).
The first queue depth option is always 1, which prevents the processor bus pipeline from queuing any outstanding commands. If selected, each command will only be issued after the processor has finished with the previous one. Therefore, every command will incur the maximum amount of latency. This varies from 4 clock cycles for a 4-stage pipeline to 12 clock cycles for pipelines with 12 stages.
In most cases, it is highly recommended that you enable command queuing by selecting the option of 4 / 8 / 12 or in some cases, Enabled. This allows the processor bus pipeline to mask its latency by queuing outstanding commands. You can expect a significant boost in performance with this feature enabled.
Interestingly, this feature can also be used as an aid in overclocking the processor. Although the queuing of commands brings with it a big boost in performance, it may also make the processor unstable at overclocked speeds. To overclock beyond what’s normally possible, you can try disabling command queuing.
But please note that the performance deficit associated with deeper pipelines (8 or 12 stages) may not be worth the increase in processor overclockability. This is because the deep processor bus pipelines have very long latencies. If they are not masked by command queuing, the processor may be stalled so badly that you may end up with poorer performance even if you are able to further overclock the processor. So, it is recommended that you enable command queuing for deep pipelines, even if it means reduced overclockability.
Hyper-Threading Technology
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the Intel Hyper-Threading Technology.
The Intel Hyper-Threading Technology allows a single processor to execute two or more separate threads concurrently. When hyper-threading is enabled, multi-threaded software applications can execute their threads in parallel, thereby improving their performance.
The Intel Hyper-Threading Technology is only supported by the Intel Pentium 4 (officially only those 3.06GHz and faster) and the Intel Xeon processors. Please note that for Hyper-Threading to work, you should have the following :-
– an Intel processor that supports Hyper-Threading
– a motherboard with a chipset and BIOS that support Hyper-Threading
– an operating system which supports Hyper-Threading (Microsoft Windows XP or Linux 2.4.x)
Since it behaves like two separate processors with their own APICs, you should also enable APIC Function in the BIOS, which is required for multi-processing.
It is highly recommended that you enable Hyper-Threading Technology for improved processor performance.
In-Order Queue Depth
Common Options : 1, 4, 8, 12
Quick Review
This BIOS feature controls the use of the processor bus’ command queue. Normally, there are only two options available. Depending on the motherboard chipset, the options could be (1 and 4), (1 and 8) or (1 and 12).
The first queue depth option is always 1, which prevents the processor bus pipeline from queuing any outstanding commands. If selected, each command will only be issued after the processor has finished with the previous one. Therefore, every command will incur the maximum amount of latency. This varies from 4 clock cycles for a 4-stage pipeline to 12 clock cycles for pipelines with 12 stages.
In most cases, it is highly recommended that you enable command queuing by selecting the option of 4 / 8 / 12 or in some cases, Enabled. This allows the processor bus pipeline to mask its latency by queuing outstanding commands. You can expect a significant boost in performance with this feature enabled.
Interestingly, this feature can also be used as an aid in overclocking the processor. Although the queuing of commands brings with it a big boost in performance, it may also make the processor unstable at overclocked speeds. To overclock beyond what’s normally possible, you can try disabling command queuing.
But please note that the performance deficit associated with deeper pipelines (8 or 12 stages) may not be worth the increase in processor overclockability. This is because the deep processor bus pipelines have very long latencies. If they are not masked by command queuing, the processor may be stalled so badly that you may end up with poorer performance even if you are able to further overclock the processor. So, it is recommended that you enable command queuing for deep pipelines, even if it means reduced overclockability.
IOQD
Common Options : 1, 4, 8, 12
Quick Review
This BIOS feature controls the use of the processor bus’ command queue. Normally, there are only two options available. Depending on the motherboard chipset, the options could be (1 and 4), (1 and 8) or (1 and 12).
The first queue depth option is always 1, which prevents the processor bus pipeline from queuing any outstanding commands. If selected, each command will only be issued after the processor has finished with the previous one. Therefore, every command will incur the maximum amount of latency. This varies from 4 clock cycles for a 4-stage pipeline to 12 clock cycles for pipelines with 12 stages.
In most cases, it is highly recommended that you enable command queuing by selecting the option of 4 / 8 / 12 or in some cases, Enabled. This allows the processor bus pipeline to mask its latency by queuing outstanding commands. You can expect a significant boost in performance with this feature enabled.
Interestingly, this feature can also be used as an aid in overclocking the processor. Although the queuing of commands brings with it a big boost in performance, it may also make the processor unstable at overclocked speeds. To overclock beyond what’s normally possible, you can try disabling command queuing.
But please note that the performance deficit associated with deeper pipelines (8 or 12 stages) may not be worth the increase in processor overclockability. This is because the deep processor bus pipelines have very long latencies. If they are not masked by command queuing, the processor may be stalled so badly that you may end up with poorer performance even if you are able to further overclock the processor. So, it is recommended that you enable command queuing for deep pipelines, even if it means reduced overclockability.

K7 CLK_CTL Select
Common Options : Default, Optimal
Quick Review
As the name suggests, this is an AMD-specific BIOS feature. It controls the Clock Control (CLK_CTL) Model Specific Register (MSR) which is part of the AMD Athlon’s power management control system.
Now, unlike the Intel Pentium 4 processor, the Athlon processor saves power by actually reducing its internal clock speed. The Athlon bus clock speed remains constant but by using an internal clock divider, the Athlon processor can reduce its internal clock speed to 1/64th (Palomino cores and older) or 1/8th (Thoroughbred cores and newer) of its nominal clock speed.
The older Athlons have a bug (Errata No. 11) called PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail. What happens is the processor can sometimes overshoot the nominal clock speed when it ramps up after a power-saving session. This causes a reduction in the Athlon bus’ I/O drive strength levels which the auto-compensation circuitry will attempt to correct. But because there is not enough time, the proper drive strengths cannot be attained before the processor reconnects to the system bus. This causes the system bus to fail, which results in a system hang.
This bug is particularly prominent in the older Athlons that use the 1/64 internal divider because they normally require a longer ramp-up time which increases the chance for the processor to overshoot the nominal clock speed. Hence, a workaround for this bug was devised whereupon the BIOS will manually reprogram the CLK_CTL register to reduce the ramp-up time.
By default, the BIOS programs the CLK_CTL register with a value of 6003_1223h during the POST routine. To increase the ramp-up speed, the BIOS has to change the value to 2003_1223h.
This is where the K7 CLK_CTL Select BIOS feature comes in. When set to Default, the BIOS will program the CLK_CTL register with a value of 6003_1223h. Setting to Optimal causes the BIOS to program the CLK_CTL register with a value of 2003_1223h.
If you are using an AMD Athlon processor with a Palomino or older core, it is recommended that you set K7 CLK_CTL Select to Optimal. This will prevent Errata No. 11 from manifesting itself and may even provide a speed boost by allowing the processor to disconnect and connect to the system bus faster.
From the Thoroughbred-A core (CPUID 680) onwards, AMD started using an internal clock divider of only 1/8 with the CLK_CTL value of 6003_1223h. This neatly circumvents the Errata No. 11 problem although AMD also corrected that bug. With such processors, the CLK_CTL should be set to the Default value of 6003_1223h.
Unfortunately, AMD then did an about-turn with the Thoroughbred-B core (CPUID 681) and changed the value associated with the 1/8 divider from 6003_1223h to 2003_1223h. Unless the BIOS was updated to recognize this difference, it would probably write the 6003_1223h value used for the Thoroughbred-A core into the register, instead of the correct 2003_1223h required by the Thoroughbred-B core. When this happens, the processor may become unstable during transitions from sleep mode to active mode.
Therefore, for Throughbred-B cores and above, you should set the K7 CLK_CTL Select BIOS feature to Optimal setting to ensure proper setting of the internal clock divider.
L3 Cache
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the functionality of the processor’s Level 3 cache.
When enabled, the processor’s Level 3 cache will be allowed to function. This allows the best possible performance from the processor.
When disabled, the processor’s Level 3 cache will be disabled. The processor will bypass the Level 3 cache and rely only on the Level 1 and Level 2 caches. This reduces the performance of the processor.
The recommended setting is obviously Enabled since disabling it severely affects the processor’s performance. However, the Disabled setting is useful as a troubleshooting tool, especially when you are overclocking your processor.
Level 2 Cache Latency
Common Options : Auto, 1 to 15
Quick Review
This BIOS feature enables you to change the latency of the processor’s Level 2 cache. By default, this feature is set to Auto which means that the processor’s Level 2 cache will be left to its default latency setting. This is the safest option.
You can also manually select the latency of the cache. For this purpose, this BIOS feature provides options ranging from 1 clock cycle to 15 clock cycles. Please note that setting too low a latency can cause the Level 2 cache to lose data integrity or fail altogether. This will manifest as a system crash or an inability to boot-up at all.
Therefore, it is recommended that you start with a high latency and work your way down until you start to encounter stability issues. This allows you to figure out the lowest latency your processor’s Level 2 cache can support. Select that latency for optimal performance without stability issues.
Please note that this is a processor-dependent feature. Not all processors support BIOS manipulation of the Level 2 cache latency. If the processor does not allow any manipulation of its Level 2 cache latency, this BIOS feature will not have any effect, irrespective of what was selected.
N/B Strap CPU As
Common Options : By CPU, PSB400, PSB533, PSB800
Quick Review
This BIOS feature allows you to circumvent the CPU-to-DRAM ratio limitation found in the newer Intel i865/i875-series of chipsets. In those chipsets, Intel has chosen to limit the choices of available CPU-to-DRAM ratios.
When a 400MHz FSB processor is installed, the choice of CPU-to-DRAM ratio is limited to 3:4.
When a 533MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1 or 4:5.
When a 800MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1, 3.2 or 5:4.
Fortunately, this BIOS feature allows you to circumvent that limitation.
The N/B Strap CPU As BIOS feature actually controls the setting of the external hardware reset strap assigned to the MCH (Memory Controller Hub) of the chipset. By setting it to PSB400, PSB533 or PSB800, you can trick the chipset into thinking that the 400MHz FSB or 533MHz FSB or the 800MHz FSB is being used.
When this BIOS feature is set to PSB800, you will be able to access the 800MHz CPU-to-DRAM ratios of 1:1, 3.2 and 5:4.
When this BIOS feature is set to PSB533, you will be able to access the 533MHz CPU-to-DRAM ratios of 1:1 and 4:5.
When this BIOS feature is set to PSB400, you will be able to access the 400MHz CPU-to-DRAM ratio of 3:4.
By default, this BIOS feature is set to By CPU, whereby the hardware strap will be set according to the actual FSB rating of the processor.
Generally, you do not need to manually adjust the hardware strap setting. But if you require access to the CPU-to-DRAM ratio that would normally not be available to you, then this BIOS feature would be very helpful indeed.

Processor Number Feature
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to control the use of the processor’s embedded unique identification number. Therefore, it is only valid if you are using a processor that features such a feature.
This infamous “feature” debuted in the Intel Pentium III processor and is mainly found only in that processor. The Transmeta Crusoe processor also supports this feature. But most manufacturers have refrained from integrating such a “feature” in their processors. Even Intel has declined to add this feature to the Intel Pentium 4 processors.
If enabled, the processor’s identification number can be read by external programs. It used to be required for certain secure transactions. However, this is no longer true as the initiative has long been abandoned.
If disabled, the processor’s identification number cannot be read by external programs.
It is highly advisable that you disable this feature because it no longer has a use. Even worse, it can actually be misused to track your online activities. Disabling this feature will safeguard your privacy by preventing the identification of your computer by the processor’s identification number.
S2K Bus Driving Strength
Common Options : Auto, Manual
Quick Review
This BIOS feature determines if the motherboard chipset should automatically adjust the drive strength of the Athlon processor bus or allow manual configuration.
If you set this feature to Auto, the chipset is allowed to dynamically adjust the S2K bus strength or use values pre-set by the manufacturer.
If you set this feature to Manual, the chipset’s dynamic compensation circuitry for the S2K bus is turned off. You can then manually set the S2K bus strength.
Generally, it is recommended that you set this feature to Auto so that the S2K bus strength can be dynamically adjusted by the chipset. However, there may be occasions when manual configuration of the S2K bus driving strength may be desirable.
It is possible to make use of this feature for overclocking purposes. Increasing the drive strength increases the stability of the S2K bus. But please be very, very circumspect when you increase the S2K bus drive strength with an overclocked processor as you may be irreversibly damage the processor!
If you wish to manually configure the S2K bus driving strength, you must set the S2K Bus Driving Strength to Manual. This allows you to manually set the S2K bus driving strength value via the S2K Strobe P Control and S2K Strobe N Control BIOS features.
S2K Strobe N Control
Common Options : 0 to F (Hex numbers), 0h to Fh
Quick Review
This BIOS feature determines the N transistor drive strength of the S2K bus.
The N transistor drive strength is represented by Hex values from 0 to F (0 to 15 in decimal). The default N transistor drive strength differs from motherboard to motherboard. But the higher the drive strength, the greater the compensation for the motherboard’s impedance on the S2K bus.
Due to the nature of this BIOS feature, it is possible to use it as an aid in overclocking the S2K bus. A higher N (and P) transistor drive strength may just be what you need to overclock the S2K bus higher than is normally possible. By raising the drive strength of the S2K bus, you can improve its stability at overclocked speeds.
Please be very, very circumspect when you increase the S2K drive strength with an overclocked processor as you may be irreversibly damage the processor!
Also, contrary to popular opinion, increasing the S2K drive strength will not improve the performance of your AMD processor. It is not a performance enhancing feature so you should not increase the N transistor drive strength unnecessarily.
S2K Strobe P Control
Common Options : 0 to F (Hex numbers), 0h to Fh
Quick Review
This BIOS feature determines the P transistor drive strength of the S2K bus.
The P transistor drive strength is represented by Hex values from 0 to F (0 to 15 in decimal). The default P transistor drive strength differs from motherboard to motherboard. But the higher the drive strength, the greater the compensation for the motherboard’s impedance on the S2K bus.
Due to the nature of this BIOS feature, it is possible to use it as an aid in overclocking the S2K bus. A higher P (and N) transistor drive strength may just be what you need to overclock the S2K bus higher than is normally possible. By raising the drive strength of the S2K bus, you can improve its stability at overclocked speeds.
Please be very, very circumspect when you increase the S2K drive strength with an overclocked processor as you may be irreversibly damage the processor!
Also, contrary to popular opinion, increasing the S2K drive strength will not improve the performance of your AMD processor. It is not a performance enhancing feature so you should not increase the P transistor drive strength unnecessarily.
Speed Error Hold
Common Options : Enabled, Disabled
Quick Review
This BIOS feature prevents accidental overclocking by preventing the system from booting up if the processor clock speed was not properly set.
When enabled, the BIOS will check the processor clock speed at boot up and halt the boot process if the clock speed is different from that imprinted in the processor ID. It will also display an error message to warn you that the processor is running at the wrong speed.
If you are thinking of overclocking the processor, you must disable this feature as it prevents the motherboard from booting up with an overclocked processor. When disabled, the BIOS will not check the processor clock speed at boot up. It will allow the system to boot with the clock speed set in the BIOS, even if it does not match the processor’s rated clock speed (as imprinted in the processor ID).
Although this may seem really obvious, I have seen countless overclocking initiates puzzling over the error message whenever they try to overclock their processors. So, before you start pulling your hair out and screaming hysterically that Intel or AMD has finally implemented a clock speed lock on their processors, try disabling this feature. 😉
Storage Subsystem

32-bit Disk Access
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to command the IDE controller to combine two 16-bit hard disk reads into a single 32-bit data transfer to the processor. This greatly improves the performance of the IDE controller as well as the PCI bus.
Therefore, it is highly advisable to enable 32-bit Disk Access. If you disable it, data transfers from the IDE controller to the processor will only occur in 16-bits chunks.

32-bit Transfer Mode
Common Options : On, Off
Quick Review
This BIOS feature allows you to command the IDE controller to combine two 16-bit hard disk reads into a single 32-bit data transfer to the processor. This greatly improves the performance of the IDE controller as well as the PCI bus.
Therefore, it is highly advisable to enable 32-bit Transfer Mode. If you disable it, data transfers from the IDE controller to the processor will only occur in 16-bits chunks.
ATA100RAID IDE Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature enables or disables the motherboard’s external UltraDMA/100 IDE RAID controller.
When enabled, the external UltraDMA/100 IDE RAID controller will be enabled to provide an additional two IDE channels and RAID capabilities.
When disabled, the external UltraDMA/100 IDE RAID controller will be disabled, freeing up two IRQs and speeding up system initialization.
It is recommended that you enable this feature if you require the use of the external UltraDMA/100 IDE RAID controller but disable it if you don’t use it.
HDD S.M.A.R.T. Capability
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls support for the hard disk’s S.M.A.R.T. (Self Monitoring Analysis And Reporting Technology) capability.
S.M.A.R.T. is supported by all current hard disks and it allows the early prediction and warning of impending hard disk disasters. You should enable it if you want to use S.M.A.R.T.-aware utilities to monitor the hard disk’s condition. Enabling it also allows the monitoring of the hard disk’s condition over a network.
While S.M.A.R.T. looks like a really great safety feature, it isn’t really that useful or even necessary for most users. For S.M.A.R.T. to work, it is not just a matter of enabling it in the BIOS. You must also keep a S.M.A.R.T.-aware hardware monitoring utility running in the background all the time.
That’s quite alright if the hard disk you are using has a spotty reputation and you need advanced warning of any impending failure. However, hard disks these days are mostly reliable enough to make S.M.A.R.T. redundant. Unless you are running mission-critical applications, it is very unlikely that S.M.A.R.T. will be of any use at all.
With that said, S.M.A.R.T. is still useful in providing a modicum of data loss prevention by continuously monitoring hard disks for signs of impending failure. If you have critical or irreplaceable data, you should enable this BIOS feature and use a S.M.A.R.T.-aware hardware monitoring software. Just don’t rely completely on it! Back up your data on a CD or DVD!
Please note that even if you do not use any S.M.A.R.T.-aware utility, enabling S.M.A.R.T. in the BIOS uses up some bandwidth because the hard disk will continuously send out data packets. So, if you do not use S.M.A.R.T.-aware utilities or if you do not need that level of real-time reporting, disable HDD S.M.A.R.T. Capability for better overall performance.
Some of the newer BIOSes now come with S.M.A.R.T. monitoring support built-in. When you enable HDD S.M.A.R.T. Capability, these new BIOSes will automatically check the hard disk’s S.M.A.R.T. status at boot-up. However, such a feature has very limited utility as it can only tell you the status of the hard disk at boot-up. Therefore, it is still advisable for you to disable HDD S.M.A.R.T. Capability unless you use a proper S.M.A.R.T.-aware monitoring utility.
IDE Bus Master Support
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is a misnomer since it doesn’t actually control the bus mastering ability of the onboard IDE controller. It is actually a toggle for the built-in driver that allows the onboard IDE controller to perform DMA (Direct Memory Access) transfers.
When this BIOS feature is enabled, the BIOS loads up the 16-bit busmastering driver for the onboard IDE controller. This allows the IDE controller to transfer data via DMA, resulting in greatly improved transfer rates and lower CPU utilization in real mode DOS and during the loading of other operating systems.
When this BIOS feature is disabled, the BIOS will not load up the 16-bit busmastering driver for the onboard IDE controller. The IDE controller will then transfer data via PIO.
Therefore, it is recommended that you enable IDE Bus Master Support. This greatly improves the IDE transfer rate and reduces the CPU utilization during the booting process or when you are using real mode DOS. Users of DOS-based disk utilities like Norton Ghost can expect to benefit a lot from this feature.

IDE HDD Block Mode
Common Options : Enabled, Disabled
Quick Review
This BIOS feature speeds up hard disk access by transferring multiple sectors of data per interrupt instead of using the usual single-sector transfer mode. This mode of transferring data is known as block transfers.
When you enable this feature, the BIOS will automatically detect if your hard disk supports block transfers and set the proper block transfer settings for it. Depending on the IDE controller, up to 64KB of data can be transferred per interrupt when block transfers are enabled. Since all current hard disks support block transfers, there is usually no reason why IDE HDD Block Mode should be disabled.
Please note that if you disable IDE HDD Block Mode, only 512 bytes of data can transferred per interrupt. Needless to say, this will significantly degrade performance.
Therefore, you should disable IDE HDD Block Mode only if you actually face the possibility of data corruption (with an unpatched version of Windows NT 4.0). Otherwise, it is highly recommended that you enable this BIOS feature for significantly better hard disk performance!
Master Drive PIO Mode
Common Options : Auto, 0, 1, 2, 3, 4
Quick Review
This BIOS feature allows you to set the PIO (Programmed Input/Output) mode for the Master IDE drive attached to that particular IDE channel.
Setting this BIOS feature to Auto lets the BIOS auto-detect the IDE drive’s maximum supported PIO mode at boot-up.
Setting this BIOS feature to 0 forces the BIOS to use PIO Mode 0 for the IDE drive.
Setting this BIOS feature to 1 forces the BIOS to use PIO Mode 1 for the IDE drive.
Setting this BIOS feature to 2 forces the BIOS to use PIO Mode 2 for the IDE drive.
Setting this BIOS feature to 3 forces the BIOS to use PIO Mode 3 for the IDE drive.
Setting this BIOS feature to 4 forces the BIOS to use PIO Mode 4 for the IDE drive.
Normally, you should leave it as Auto and let the BIOS auto-detect the IDE drive’s PIO mode. You should only set it manually for the following reasons :-
 if the BIOS cannot detect the correct PIO mode.
 if you want to try forcing the IDE device to use a faster PIO mode than it was designed for.
 if you want to force the IDE device to use a slower PIO mode if it cannot work properly with the current PIO mode (i.e. when the PCI bus is overclocked)
Please note that forcing an IDE device to use a PIO transfer rate that is faster than what it is rated for can potentially cause data corruption.
Master Drive UltraDMA
Common Options : Auto, Disabled
Quick Review
This BIOS feature allows you to enable or disable DMA (Direct Memory Access) support (if available) for the Master IDE device attached to that particular IDE channel.
Setting this BIOS feature to Auto lets the BIOS auto-detect the IDE drive’s maximum supported DMA mode at boot-up.
Setting this BIOS feature to Disabled forces the BIOS to disable DMA transfers for the IDE drive.
Normally, you should leave it as Auto and let the BIOS auto-detect the drive’s DMA support. If the drive supports DMA transfers, the proper DMA transfer mode will be enabled for that drive, allowing it to burst data at anywhere from 33MB/s to 133MB/s (depending on the transfer mode supported).
You should only disable it for troubleshooting purposes. For example, certain IDE devices may not run properly using DMA transfers when the PCI bus is overclocked. Disabling DMA support will force the drive to use the slower PIO transfer mode. This may allow the drive to work properly with the higher PCI bus speed.
Please note that setting this to Auto will not enable DMA transfers for IDE devices that do not support DMA transfers. If your drive does not support DMA transfers, the BIOS will automatically set the drive to do PIO transfers only.
Also note that this BIOS feature merely enables DMA transfers during the booting up process and for operating systems that do not load their own drivers for IDE functions. For operating systems that use their own IDE drivers (i.e. Windows 9x / 2000 / XP), you have to enable DMA support for the drive within the operating system as well.

Onboard FDD Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to enable or disable the onboard floppy drive controller.
When enabled, the motherboard’s onboard floppy drive controller will be enabled.
When disabled, the motherboard’s onboard floppy drive controller will be disabled. This frees up the IRQ used by the floppy drive controller.
If you are using a floppy drive connected to the motherboard’s built-in floppy drive controller, select the Enabled option.
If you are using an add-on floppy drive controller card or if you are not using any floppy drive at all, set it to Disabled to save an IRQ which can be used by other devices.
Onboard IDE-1 Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is actually a misnomer because there is only one IDE controller integrated into current chipsets.
This single IDE controller comes with two IDE channels, each of which supports up to two IDE drives. Therefore, the IDE controller supports a total of four IDE devices through two IDE channels.
When enabled, the IDE channel will be able to provide support for up to two IDE drives.
When disabled, the IDE channel will be disabled. Any attached IDE drives will not be accessible. However, this frees up an IRQ, which can be used by other devices. Disabling this IDE channel will also speed up the booting sequence a little as the BIOS will not need to query this channel for IDE devices when it boots up.
You should leave this enabled if you are using this IDE channel. Disabling it will prevent any IDE devices attached to this channel from being accessed.
If you are not attaching any IDE devices to this IDE channel (or if you are using a SCSI / an add-on IDE card), you can disable this IDE channel to free an IRQ and speed up the booting sequence.

Onboard IDE-2 Controller
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is actually a misnomer because there is only one IDE controller integrated into current chipsets.
This single IDE controller comes with two IDE channels, each of which supports up to two IDE drives. Therefore, the IDE controller supports a total of four IDE devices through two IDE channels.
When enabled, the IDE channel will be able to provide support for up to two IDE drives.
When disabled, the IDE channel will be disabled. Any attached IDE drives will not be accessible. However, this frees up an IRQ, which can be used by other devices. Disabling this IDE channel will also speed up the booting sequence a little as the BIOS will not need to query this channel for IDE devices when it boots up.
You should leave this enabled if you are using this IDE channel. Disabling it will prevent any IDE devices attached to this channel from being accessed.
If you are not attaching any IDE devices to this IDE channel (or if you are using a SCSI / an add-on IDE card), you can disable this IDE channel to free an IRQ and speed up the booting sequence.
PCI IDE Busmaster
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is a misnomer since it doesn’t actually control the bus mastering ability of the onboard IDE controller. It is actually a toggle for the built-in driver that allows the onboard IDE controller to perform DMA (Direct Memory Access) transfers.
When this BIOS feature is enabled, the BIOS loads up the 16-bit busmastering driver for the onboard IDE controller. This allows the IDE controller to transfer data via DMA, resulting in greatly improved transfer rates and lower CPU utilization in real mode DOS and during the loading of other operating systems.
When this BIOS feature is disabled, the BIOS will not load up the 16-bit busmastering driver for the onboard IDE controller. The IDE controller will then transfer data via PIO.
Therefore, it is recommended that you enable PCI IDE Busmaster. This greatly improves the IDE transfer rate and reduces the CPU utilization during the booting process or when you are using real mode DOS. Users of DOS-based disk utilities like Norton Ghost can expect to benefit a lot from this feature.
Swap Floppy Drive
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is used to logically swap the mapping of drives A: and B:. Therefore, it is only useful if you have two floppy drives.
Normally, the sequence by which you connect the floppy drives to the cable determines which is drive A: and which is drive B:. If you attach the floppy drives the wrong way and obtain a drive mapping that is not to your satisfaction, the usual way of correcting this is to physically swap the floppy cable connectors.
This feature allows you to swap the logical arrangement of the floppy drives without the need to open up the case and physically swap the connectors.
When this BIOS feature is enabled, the floppy drive that originally was mapped to drive A: will be remapped to drive B: and vice versa for the drive that was originally set as drive B:.
When this BIOS feature is disabled, the floppy drive mapping will remain as that set by the drive connector arrangement.
Although this appears to be nothing more than a feature of convenience, it can be quite important if you are using two floppy drives of different form factors (3.5″ and 5.25″) and you need to boot from the second drive. Because the BIOS can only boot from drive A:, you will have to physically swap the drive connections or use BIOS this feature to do it logically.
If your floppy drive mapping is correct or if you only have a single floppy drive, there is no need to enable this feature. Leave it at the default setting of disabled.
System Bus
16-bit I/O Recovery Time
Common Options : NA, 4, 1, 2, 3
Quick Review
This BIOS feature allows you to add extra wait cycles between consecutive 16-bit PCI cycles to the ISA bus. This is used to correct timing issues between the PCI bus and ISA bus.
Please note that there is already a fixed minimum delay of 3.5 clock cycles so whatever you set using this BIOS feature adds to that delay. Choosing NA sets the number of delay cycles to the minimum 3.5 clock cycles.
Most 16-bit ISA cards will work fine with the minimum 3.5 delay cycles (NA). However, if your ISA card cannot work properly, try increasing the number of additional delay cycles.
8-bit I/O Recovery Time
Common Options : NA, 8, 1, 2, 3, 4, 5, 6, 7
Quick Review
This BIOS feature allows you to add extra wait cycles between consecutive 8-bit PCI cycles to the ISA bus. This is used to correct timing issues between the PCI bus and ISA bus.
Please note that there is already a fixed minimum delay of 3.5 clock cycles so whatever you set using this BIOS feature adds to that delay. Choosing NA sets the number of delay cycles to the minimum 3.5 clock cycles.
Most 8-bit ISA cards will work fine with the minimum 3.5 delay cycles (NA). However, if your ISA card cannot work properly, try increasing the number of additional delay cycles.
AT Bus Clock
Common Options : 7.16MHz, CLK/2, CLK/3, CLK/4, CLK/5, CLK/6
Quick Review
This BIOS feature allows you to select the ISA bus’ clock speed. The chipset actually generates the ISA bus clock by dividing the PCI clock. Hence, the available settings of CLK/2, CLK/3, CLK/4, CLK/5 and CLK/6.
There is also the fixed speed of 7.16MHz which is derived by dividing the reference clock generator speed of 14.318MHz by a factor of two.
As you can see, the setting of CLK/4 yields an ISA bus speed of 8.33MHz which is the maximum speed allowed by the official ISA specifications. However, you can choose to overclock the ISA by by selecting the settings of CLK/3 and CLK/2 which yield clock speeds of 11.11MHz and 16.67MHz respectively.
Overclocking the ISA bus greatly improves its performance. Therefore, it is recommended that you try to use the faster settings if possible. However, while newer ISA cards are capable of running at this ‘out-of-spec’ speed, older ones may not work properly at this speed.
If your ISA cards fail to work properly, then you should select the setting of CLK/4 or 7.16MHz. That will keep the ISA bus within specifications.
Please note that the calculations and recommendations above were based on a 33MHz PCI bus clock. If you are overclocking your PCI bus, please take the increased PCI clock speed into account!
If all this is confusing and you want to play safe, select the setting of 7.16MHz. That is the fail-safe setting because it will set the ISA bus to run at a fixed speed of 7.16MHz, irrespective of the PCI bus speed.
Auto Detect DIMM/PCI Clk
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the BIOS should actively reduce EMI (Electromagnetic Interference) and reduce power consumption by turning off unoccupied or inactive expansion slots.
When enabled, the BIOS will monitor AGP, PCI and memory slots and turn off clock signals to all unoccupied and inactive slots.
When disabled, the BIOS will not monitor AGP, PCI and memory slots. All clock signals will remain active even to unoccupied or inactive slots.
It is recommended that you enable this feature to save power and reduce EMI.
Byte Merge
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is similar to the PCI Dynamic Bursting feature.
When enabled, the PCI write buffer accumulates and merges 8-bit and 16-bit writes into 32-bit writes. This increases the efficiency of the PCI bus and improves its bandwidth.
When disabled, the PCI write buffer will not accumulate or merge 8-bit or 16-bit writes. It will just write them to the PCI bus as soon as the bus is free. As such, there may be a loss of PCI bus efficiency when 8-bit or 16-bit data is written to the PCI bus.
Therefore, it is recommended that you enable Byte Merge for better performance.
However, please note that Byte Merge may be incompatible with certain PCI network interface cards (also known as NICs). So, if your NIC won’t work properly, try disabling this feature.
CPU to PCI Post Write
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the chipset’s CPU-to-PCI write buffer. It is used to store PCI writes from the processor before they are written to the PCI bus.
When enabled, all PCI writes from the processor will go directly to the write buffer. This allows the processor to work on something else while the write buffer writes the data to the PCI bus on the next available PCI cycle.
When disabled, the processor bypasses the buffer and writes directly to the PCI bus. This ties up the processor for the entire length of the transaction.
It is recommended that you enable this BIOS feature for better performance.
CPU to PCI Write Buffer
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the chipset’s CPU-to-PCI write buffer. It is used to store PCI writes from the processor before they are written to the PCI bus.
When enabled, all PCI writes from the processor will go directly to the write buffer. This allows the processor to work on something else while the write buffer writes the data to the PCI bus on the next available PCI cycle.
When disabled, the processor bypasses the buffer and writes directly to the PCI bus. This ties up the processor for the entire length of the transaction.
It is recommended that you enable this BIOS feature for better performance.
Delayed Transaction
Common Options : Enabled, Disabled
Quick Review
To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed. According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles for the initial read and 8 PCI clock cycles for each subsequent read.
If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Delayed Transaction feature.
With PCI Delayed Transaction enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.
If the delayed transaction is a write, the master device will rearbitrate for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, the target device just sends the completion status to the master device to complete the transaction.
One advantage of using PCI Delayed Transaction is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.
PCI Delayed Transaction also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. Without PCI Delayed Transaction, all write-posted data will have to be flushed before another PCI transaction can occur.
It is highly recommended that you enable Delayed Transaction for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.
Please note that while many manuals and even earlier versions of the BIOS Optimization Guide have stated that this is an ISA bus-specific BIOS feature which enables a 32-bit write-posted buffer for faster PCI-to-ISA writes, they are incorrect! This BIOS feature is not ISA bus-specific and it does not control any write-posted buffers. It merely allows write-posting to continue while a non-postable PCI transaction is underway.
Disable Unused PCI Clock
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the BIOS should actively reduce EMI (Electromagnetic Interference) and reduce power consumption by turning off unoccupied or inactive PCI slots.
When enabled, the BIOS will monitor PCI slots and turn off clock signals to all unoccupied and inactive slots.
When disabled, the BIOS will not monitor PCI slots. All clock signals will remain active even to unoccupied or inactive slots.
It is recommended that you enable this feature to save power and reduce EMI.
FSB Spread Spectrum
Common Options : 0.5%, 1.0%, Disabled
Quick Review
This BIOS feature allows you to reduce the EMI of the front side bus (known alternately as the FSB or processor bus) by modulating the signals it generates so that the spikes are reduced to flatter curves. It achieves this by varying the frequency slightly so that the signal does not use any particular frequency for more than a moment.
The BIOS usually offers two levels of modulation – 0.5% or 1.0%. The greater the modulation, the greater the reduction of EMI. Therefore, if you need to significantly reduce the front side bus’ EMI, a modulation of 1.0% is recommended.
In most conditions, frequency modulation via this feature should not cause any problems. However, system stability may be compromised if you are overclocking the front side bus. Of course, this depends on the amount of modulation, the extent of overclocking and other factors like temperature, etc. As such, the problem may not readily manifest itself immediately.
Therefore, it is recommended that you disable this feature if you are overclocking the front side bus. The risk of crashing your system is not worth the reduction in EMI. Of course, if EMI reduction is important to you, enable this feature by all means. But you should reduce the clock speed a little to provide a margin of safety.
If you are not overclocking, the decision to enable or disable this feature is really up to you. But unless you have EMI problems or sensitive data that must be safeguarded from electronic eavesdropping, it is best to disable this feature to remove the possibility of stability issues.
ISA 14.318MHz Clock
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to overclock the ISA bus using the reference clock generator speed of 14.318MHz. This greatly improves the ISA bus speed by running the bus 72% faster than normal. At this clock speed, 8-bit cards will have a bandwidth of 7.16MB/s while 16-bit cards will have a bandwidth of 14.32MB/s.
In most cases, it is recommended that you enable this feature to give the ISA bus a performance boost. Of course, this is only useful if you have ISA devices in your system. Otherwise, this feature is redundant.
Please note that while newer ISA cards are capable of running at this ‘out-of-spec’ speed, older ones may not work properly at this speed. Therefore, if your ISA card fails to function properly, disable this feature.
ISA Enable Bit
Common Options : Enabled, Disabled
Quick Review
This BIOS feature allows you to determine if the system controller will perform ISA aliasing to prevent conflicts between ISA devices.
The default setting of Enabled forces the system controller to alias ISA addresses using address bits [15:10]. This restricts all 16-bit addressing devices to a maximum contiguous I/O space of 256 bytes.
When disabled, the system controller will not perform any ISA aliasing and all 16 address lines can be used for I/O address space decoding. This gives 16-bit addressing devices access to the full 64KB I/O space.
It is recommended that you disable ISA Enable Bit for optimal AGP (and PCI) performance. It will also prevent your AGP or PCI cards from conflicting with your ISA cards. Enable it only if you have ISA devices that are conflicting with each other.
Master Priority Rotation
Common Options : 1 PCI, 2 PCI, 3 PCI
Quick Review
This BIOS feature controls the priority of the processor’s accesses to the PCI bus.
If you choose 1 PCI, the processor will always be granted access right after the current PCI bus master completes its transaction, irrespective of how many other PCI bus masters are on the queue.
If you choose 2 PCI, the processor will always be granted access right after the second PCI bus master on the queue completes its transaction.
If you choose 3 PCI, the processor will always be granted access right after the third PCI bus master on the queue completes its transaction.
But no matter what you choose, the processor is guaranteed access to the PCI bus after a certain number of PCI bus master grants. It doesn’t matter if there are numerous PCI bus masters on the queue or when the processor requests access to the PCI bus. The processor will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).
For better overall performance, it is recommended that you select the 1 PCI option as this allows the processor to access the PCI bus with minimal delay. However, if you wish to improve the performance of your PCI devices, you can try the 2 PCI or 3 PCI options. They ensure that your PCI cards will receive greater PCI bus priority.
P2C/C2P Concurrency
Common Options : Enabled, Disabled
Quick Review
The BIOS feature allows PCI-to-CPU and CPU-to-PCI traffic to occur concurrently. This means PCI traffic to the CPU and CPU traffic to the PCI bus can occur simultaneously.
This prevents the CPU from being “locked up” during PCI transfers. It also allows PCI traffic to the processor to occur without delay even when the processor is writing to the PCI bus. This may prevent performance issues with certain PCI cards.
Therefore, it is recommended that you enable this feature for better performance.
Passive Release
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls the passive release feature of the CPU to PCI Write Buffer. Therefore, if the write buffer is disabled, this BIOS feature will not have any effect. However, the reverse is not true. The CPU to PCI Write Buffer feature will still work even if Passive Release is disabled.
When Passive Release is enabled, the write buffer will independently write the data to the PCI bus at the first available opportunity. It can do so even when the processor is busy doing something else.
When Passive Release is disabled, the write buffer will wait till the processor reasserts (retries) the write request. Only then will it write to the PCI bus. This still improves performance because the processor does not need to resend the data. However, the write buffer still loses some of its effectiveness because it has to wait for the CPU to retry the transaction.
For best performance, it is highly recommended that you enable Passive Release. This will dramatically reduce the effect of slow ISA devices hogging the PCI bus. However, some ISA cards may not work well with Passive Release. In such cases, disable Passive Release or better yet, throw the card away and get a PCI version instead!
If you don’t use any ISA device, this feature should still be enabled because it allows the write buffer to offload its data to the PCI bus without waiting for the processor to retry the transaction. This improves the performance of the processor and PCI bus.
Please note again that this BIOS feature will have no effect if you disable the CPU to PCI Write Buffer.
PCI 2.1 Compliance
Common Options : Enabled, Disabled
Quick Review
To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed. According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles for the initial read and 8 PCI clock cycles for each subsequent read.
If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Delayed Transaction feature.
With PCI Delayed Transaction enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.
If the delayed transaction is a write, the master device will rearbitrate for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, the target device just sends the completion status to the master device to complete the transaction.
One advantage of using PCI Delayed Transaction is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.
PCI Delayed Transaction also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. Without PCI Delayed Transaction, all write-posted data will have to be flushed before another PCI transaction can occur.
It is highly recommended that you enable PCI 2.1 Compliance for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.
Please note that while many manuals and even earlier versions of the BIOS Optimization Guide have stated that this is an ISA bus-specific BIOS feature which enables a 32-bit write-posted buffer for faster PCI-to-ISA writes, they are incorrect! This BIOS feature is not ISA bus-specific and it does not control any write-posted buffers. It merely allows write-posting to continue while a non-postable PCI transaction is underway.
PCI Chaining
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is designed to speed up writes from the processor to the PCI bus by allowing write combining to occur at the PCI interface.
When PCI chaining is enabled, up to four quadwords of processor writes to contiguous PCI addresses will be chained together and written to the PCI bus as a single PCI burst write.
When PCI chaining is disabled, each processor write to the PCI bus will be handled as separate non-burstable writes.
Needless to say, writing four quadwords of data in a single PCI write is much faster than doing so in four separate non-burstable writes. A single PCI burst write will also reduce the amount of time the processor has to wait while writing to the PCI bus.
Therefore, it is recommended that you enable this feature for better CPU to PCI write performance.
PCI Clock / CPU FSB Clock
Common Options : 1/2, 1/3, 1/4, 1/5, 1/6
Quick Review
This BIOS feature allows you to manually select the PCI bus clock divider. Because this divider determines the speed that the PCI bus will run at, manipulation of this feature allows you some control over the PCI bus speed.
It was meant to keep the PCI bus running within specifications when you overclock the processor bus but you can also use it to overclock the PCI bus. With that said, you should keep in mind that the recommended safe limit for an overclocked PCI bus is 37.5MHz. This is the speed at which practically all new PCI cards can run at without breaking a sweat.
Selecting the clock divider of 1/2 makes the PCI bus run at half the processor bus speed. As such, this clock divider is useful for processor bus speeds of 66MHz to 75MHz.
Selecting the clock divider of 1/3 makes the PCI bus run at a third of the processor bus speed. As such, this clock divider is useful for processor bus speeds of 100MHz to 112.5MHz.
Selecting the clock divider of 1/4 makes the PCI bus run at a quarter of the processor bus speed. As such, this clock divider is useful for processor bus speeds of 133MHz to 150MHz.
Selecting the clock divider of 1/5 makes the PCI bus run at a fifth of the processor bus speed. As such, this clock divider is useful for processor bus speeds of 166MHz to 187.5MHz.
Selecting the clock divider of 1/6 makes the PCI bus run at a sixth of the processor bus speed. As such, this clock divider is useful for processor bus speeds of 200MHz to 225MHz.
You will probably be wondering about the gaps in the processor bus speeds listed above. For your convenience, only processor bus speeds that produce PCI clock speeds within the range of optimal PCI clock speeds (33MHz to 37.5MHz) are displayed above. The other processor bus speeds will either produce a slow PCI bus or an excessively overclocked one.
Therefore, for optimal PCI bus performance, try to strike for one of the processor bus speed-divider combinations shown above.

PCI Delay Transaction
Common Options : Enabled, Disabled
Quick Review
To meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed. According to this rule, a PCI 2.1-compliant device must service a read request within 16 PCI clock cycles for the initial read and 8 PCI clock cycles for each subsequent read.
If it cannot do so, the PCI bus will terminate the transaction so that other PCI devices can access the bus. But instead of rearbitrating for access (and failing to meet the minimum latency requirement again), the PCI 2.1-compliant device can make use of the PCI Delayed Transaction feature.
With PCI Delayed Transaction enabled, the target device can independently continue the read transaction. So, when the master device successfully gains control of the bus and reissues the read command, the target device will have the data ready for immediate delivery. This ensures that the retried read transaction can be completed within the stipulated latency period.
If the delayed transaction is a write, the master device will rearbitrate for bus access while the target device completes writing the data. When the master device regains control of the bus, it reissues the same write request. This time, the target device just sends the completion status to the master device to complete the transaction.
One advantage of using PCI Delayed Transaction is that it allows other PCI masters to use the bus while the transaction is being carried out on the target device. Otherwise, the bus will be left idling while the target device completes the transaction.
PCI Delayed Transaction also allows write-posted data to remain in the buffer while the PCI bus initiates a non-postable transaction and yet still adhere to the PCI ordering rules. Without PCI Delayed Transaction, all write-posted data will have to be flushed before another PCI transaction can occur.
It is highly recommended that you enable PCI Delay Transaction for better PCI performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly with this feature enabled or if you are using PCI cards that are not PCI 2.1 compliant.
Please note that while many manuals and even earlier versions of the BIOS Optimization Guide have stated that this is an ISA bus-specific BIOS feature which enables a 32-bit write-posted buffer for faster PCI-to-ISA writes, they are incorrect! This BIOS feature is not ISA bus-specific and it does not control any write-posted buffers. It merely allows write-posting to continue while a non-postable PCI transaction is underway.

PCI Dynamic Bursting
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is similar to the Byte Merge feature.
When enabled, the PCI write buffer accumulates and merges 8-bit and 16-bit writes into 32-bit writes. This increases the efficiency of the PCI bus and improves its bandwidth.
When disabled, the PCI write buffer will not accumulate or merge 8-bit or 16-bit writes. It will just write them to the PCI bus as soon as the bus is free. As such, there may be a loss of PCI bus efficiency when 8-bit or 16-bit data is written to the PCI bus.
Therefore, it is recommended that you enable PCI Dynamic Bursting for better performance.
However, please note that PCI Dynamic Bursting may be incompatible with certain PCI network interface cards (also known as NICs). So, if your NIC won’t work properly, try disabling this feature.
PCI IRQ Activated By
Common Options : Edge, Level
Quick Review
This BIOS feature allows you to set the method by which the IRQs for your PCI devices are activated or triggered.
ISA and old PCI devices are edge-triggered (using a single voltage level) while newer PCI and AGP devices are level-triggered (using multiple voltage levels). This is important mainly because PCI devices must be level-triggered to share IRQs.
Because all PCI devices currently in the market are level-triggered, it is recommended that you set this BIOS feature to Level so that your PCI devices can share IRQs.
But if you are still using old edge-triggered devices, select Edge to force the chipset to allow only edge-triggering of PCI devices. This may cause configuration problems if there are IRQ conflicts but it will prevent system lockups that can occur if the chipset erroneously attempts to level-trigger an edge-triggered PCI device.

PCI Latency Timer
Common Options : 0 – 255
Quick Review
This BIOS feature controls how long a PCI device can hold the PCI bus before another takes over. The longer the latency, the longer the PCI device can retain control of the bus before handing it over to another PCI device.
Normally, the PCI Latency Timer is set to 32 cycles. This means the active PCI device has to complete its transactions within 32 clock cycles or hand it over to the next PCI device.
For better PCI performance, a longer latency should be used. Try increasing it to 64 cycles or even 128 cycles. The optimal value for every system is different. You should benchmark your PCI cards’ performance after each change to determine the optimal PCI latency time for your system.
Please note that a longer PCI latency isn’t necessarily better. A long latency can also reduce performance as the other PCI devices queuing up may be stalled for too long. This is especially true with systems with many PCI devices or PCI devices that continuously write short bursts of data to the PCI bus. Such systems would work better with shorter PCI latencies as they allow rapid access to the PCI bus.
In addition, some time-critical PCI devices may not agree with a long latency. Such devices require priority access to the PCI bus which may not be possible if the PCI bus is held up by another device for a long period. In such cases, it is recommended that you keep to the default PCI latency of 32 cycles.
PCI Master 0 WS Read
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the chipset inserts a delay before any reads from the PCI bus.
If PCI Master 0 WS Read is enabled, read requests to the PCI bus are executed immediately (with zero wait states), if the PCI bus is ready to send data.
If PCI Master 0 WS Read is disabled, every read request to the PCI bus will be delayed by one wait state.
It is recommended that you enable this feature for better PCI read performance.
However, disabling it may be useful if you are attempting to stabilize an overclocked PCI bus. The delay will generally improve the overclockability and stability of the PCI bus.

PCI Master 0 WS Write
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines whether the chipset inserts a delay before any writes from the PCI bus.
If PCI Master 0 WS Write is enabled, write requests to the PCI bus are executed immediately (with zero wait states), if the PCI bus is ready to send data.
If PCI Master 0 WS Write is disabled, every write request to the PCI bus will be delayed by one wait state.
It is recommended that you enable this feature for better PCI write performance.
However, disabling it may be useful if you are attempting to stabilize an overclocked PCI bus. The delay will generally improve the overclockability and stability of the PCI bus.
PCI Master Read Caching
Common Options : Enabled, Disabled
Quick Review
This is an AMD-specific BIOS feature. It determines if the processor’s L2 cache will be used to cache PCI bus master reads.
If this feature is enabled, the processor’s L2 cache will be used to cache PCI bus master reads. This boosts the performance of PCI bus masters. On the other hand, it reduces the processor’s performance since it uses up some of the precious L2 cache.
This is why motherboard manufacturers like ASUS recommend that only systems using AMD Athlon processors should enable this feature. Duron users should disable this feature because its small L2 cache will not be able to cache the PCI reads without causing a massive hit to memory bandwidth.
Although the final word is still in the air, I recommend disabling this feature. The use of precious L2 cache to cache PCI bus masters is not worth the potential benefit in PCI bus performance.
PCI Pipelining
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines if PCI transactions to the memory subsystem will be pipelined.
If the PCI pipeline feature is enabled, the memory controller allows PCI transactions to be pipelined. This masks the latency of each PCI transaction and improves the efficiency of the PCI bus.
If the PCI pipeline feature is disabled, the memory controller is forced to check for outstanding transactions from other devices to the same block address that each PCI transaction is targeting.
For better PCI performance, the PCI pipeline should be enabled. This allows the latency of the bus to be masked for consecutive transactions.
However, if your system constantly locks up for no apparent reason, try disabling this feature. Disabling PCI Pipelining reduces performance but ensures that data coherency is strictly maintained for maximum reliability.
PCI Prefetch
Common Options : Enabled, Disabled
Quick Review
This feature controls the system controller’s PCI prefetch capability.
When enabled, the system controller will prefetch data whenever the PCI device reads from the system memory. This speeds up PCI reads as it allows contiguous memory reads by the PCI device to proceed with minimal delay.
Therefore, it is recommended that you enable this feature for better PCI read performance.
PCI Target Latency
Common Options : Enabled, Disabled
Quick Review
This BIOS feature determines if the system controller should conform to the PCI maximum target latency rule.
When this feature is enabled, the system controller will disconnect the PCI bus master when it cannot service a read request within 32 PCI clock cycles for the initial read and 8 PCI clock cycles for subsequent reads. The PCI bus master will then rearbitrate for access to the PCI bus.
When this feature is disabled, the PCI bus master will not be disconnected when it cannot service a read request within the stipulated 32 PCI clock cycles for the initial read and 8 PCI clock cycles for subsequent reads. The PCI bus master is allowed to complete with its transactions.
It is recommended that you enable this feature to enforce the PCI maximum target latency rule and prevent potential deadlocks.

PCI to DRAM Prefetch
Common Options : Enabled, Disabled
Quick Review
This feature controls the system controller’s PCI prefetch capability.
When enabled, the system controller will prefetch data whenever the PCI device reads from the system memory. This speeds up PCI reads as it allows contiguous memory reads by the PCI device to proceed with minimal delay.
Therefore, it is recommended that you enable this feature for better PCI read performance.
PCI#2 Access #1 Retry
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is linked to CPU to PCI Write Buffer. Therefore, if the write buffer is disabled, this BIOS feature will not have any effect. However, the reverse is not true. The CPU to PCI Write Buffer feature will still work even if PCI#2 Access #1 Retry is disabled.
When the buffer is enabled, the processor writes directly to the buffer, instead of the PCI bus. The buffer then attempts to write the data to the PCI bus by Passive Release. This allows the processor to perform other tasks without waiting for its data to be written to the PCI bus.
However, the attempted buffer write to the PCI bus may fail because the PCI bus may still be occupied by another device. When that happens, this BIOS feature determines if the buffer write should be reattempted or sent back for arbitration.
If this BIOS feature is enabled, the buffer will attempt to write to the PCI bus until it is successful.
If this BIOS feature is disabled, the buffer will flush its contents and register the transaction as failed. The processor will now have to write again to the write buffer.
Generally, it is recommended that you enable this feature as this improves the processor’s performance.
However, if you have many PCI devices and their performance is more important, you may want to disable this feature. This prevents excessive generation of retries by the write buffer which may severely tax the PCI bus. Disabling this feature will improve the PCI bus’ performance, especially with slow PCI devices that hog the bus for long periods of time at a stretch.
Please note again that this BIOS feature will have no effect if you disable the CPU to PCI Write Buffer.
Split Lock Operations
Common Options : Enabled, Disabled
Quick Review
This is a debug feature specific to the Intel Pentium 4 and the Intel Pentium 4 Xeon processors. It allows you to prevent the processor from issuing split lock cycles to the processor bus if such operations cause problems.
Split lock cycles can potentially cause problems in certain situations. For example, the Split Lock Cycles bug in the Intel 82860 MCH.
Usually, it is recommended that you leave Split Lock Operation at its default setting of Enabled. This allows the processor to issue split lock cycles to the processor bus. However, if you are using a motherboard based on the Intel 82860 chipset, you should disable this feature.
There may be other situations where split lock cycles can cause problems. If your system hangs or crashes for no apparent reason, you can try disabling this feature and see if it solves the problem. Otherwise, leave it enabled.
Synchronouse Mode Select
Common Options : Synchronous, Asynchronous
Quick Review
This BIOS feature controls the signal synchronization of the DRAM-CPU interface.
When set to Synchronous, the chipset synchronizes the signals from the DRAM controller with signals from the CPU bus (or front side bus). Please note that for the signals to be synchronous, the DRAM controller and the CPU bus must run at the same clock speed.
When set to Asynchronous, the chipset will decouple the DRAM controller from the CPU bus. This allows the DRAM controller and the CPU bus to run at different clock speeds.
Generally, it is advisable to use the Synchronous setting as a synchronized interface allows data transfers to occur without delay. This results in a much higher throughput between the CPU bus and the DRAM controller.
VLink 8X Support
Common Options : Enabled, Disabled
Quick Review
The VLink 8X Support BIOS feature is used to toggle the V-Link bus mode between the original V-Link and the newer and faster 8X V-Link.
If this feature is enabled, the quad-pumped 8-bit V-Link bus will switch to the new 8X V-Link mode, which runs at 133MHz and delivers a bandwidth of 533MB/s.
If this feature is disabled, the V-Link bus will use a clock speed of 66MHz, essentially reverting to the original V-Link standard. It will then deliver a bandwidth of 266MB/s.
This BIOS feature was most likely included for troubleshooting purposes. It is highly recommended that you enable this BIOS feature for better performance.
System Resource Management
APIC Function
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is used to enable or disable the motherboard’s APIC (Advanced Programmable Interrupt Controller). The APIC provides multiprocessor support, more IRQs and faster interrupt handling.
However, it is only supported by newer operating systems like Microsoft Windows NT, Windows 2000 and Windows XP. Older operating systems like DOS or Windows 95/98 do not support this feature.
It is recommended that you enable this feature if you are using a newer operating system like Windows XP. Disable it only if you are using an older operating system like DOS or Windows 95/98.
Assign IRQ For USB
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls whether the BIOS should assign an IRQ to the USB controller.
When enabled, an IRQ is assigned to the USB controller and you will be able to connect your USB devices to it.
When disabled, the USB controller will not be assigned an IRQ. This disables the USB controller but frees up an IRQ.
It is recommended that you enable this feature if you use USB peripherals.

Assign IRQ For VGA
Common Options : Enabled, Disabled
Quick Review
This BIOS feature controls whether the BIOS should assign an IRQ to the graphics card.
When enabled, an IRQ is assigned to the graphics card.
When disabled, the graphics card will not be assigned an IRQ.
While there are some exceptions, most graphics cards require an IRQ to work properly. Therefore, it is recommended that you enable this feature for proper operation of your graphics card.
ECP Mode Use DMA
Common Options : Channel 1, Channel 3
Quick Review
This BIOS feature determines which DMA channel the parallel port should use when it is in ECP mode.
The ECP mode uses the DMA protocol to achieve data transfer rates of up to 2.5 Mbits/s and provides symmetric bidirectional communications. For all this, it requires the use of a DMA channel.
By default, the parallel port uses DMA Channel 3 when it is in ECP mode. This works fine in most situations.
This feature was provided just in case one of your add-on cards requires the use of DMA Channel 3. In such a case, you can use this BIOS feature to force the parallel port to use the alternate DMA Channel 1.
Please note that there is no performance advantage in choosing DMA Channel 3 over DMA Channel 1 or vice versa. As long as either Channel 3 or Channel 1 is available for your parallel port to use, the parallel port will be able to function properly in ECP mode.
EPP Mode Select
Common Options : EPP 1.7, EPP 1.9
Quick Review
There are two versions of the EPP transfer protocol – EPP 1.7 and EPP 1.9. This BIOS feature allows you to select the version of EPP that the parallel port should use.
Generally, EPP 1.9 is the preferred setting because it supports the newer EPP 1.9 devices and most EPP 1.7 devices; and offers advantages like support for longer cables. However, because certain EPP 1.7 devices cannot work properly with an EPP 1.9 port, this BIOS feature was implemented to allow you to set the EPP mode to EPP 1.7 when such an issue crops up.
Therefore, it is recommended that you set this BIOS feature to EPP 1.9. But if you have trouble connecting to your parallel port device, switch to EPP 1.7
Force Update ESCD
Common Options : Enabled, Disabled
Quick Review
If you install a new piece of hardware or modify your computer’s hardware configuration, the BIOS will automatically detect the changes and reconfigure the ESCD (Extended System Configuration Data). Therefore, there is usually no need to manually force the BIOS to reconfigure the ESCD.
However, the occasion may arise where the BIOS may not be able to detect the hardware changes. A serious resource conflict may occur and the operating system may not even boot as a result. This is where the Force Update ESCD BIOS feature comes in.
This BIOS feature allows you to manually force the BIOS to clear the previously saved ESCD data and reconfigure the settings. All you need to do is enable this BIOS feature and then reboot your computer. The new ESCD should resolve the conflict and allow the operating system to load normally.
Please note that the BIOS will automatically reset it to the default setting of Disabled after reconfiguring the new ESCD. So, there is no need for you to manually disable this feature after rebooting.
Interrupt Mode
Common Options : PIC, APIC
Quick Review
This BIOS feature is used to enable or disable the motherboard’s APIC (Advanced Programmable Interrupt Controller). The APIC provides multiprocessor support, more IRQs and faster interrupt handling.
However, it is only supported by newer operating systems like Microsoft Windows NT, Windows 2000 and Windows XP. Older operating systems like DOS or Windows 95/98 do not support this feature.
It is recommended that you select APIC if you are using a newer operating system like Windows XP. Select PIC only if you are using an older operating system like DOS or Windows 95/98.
MPS Control Version For OS
Common Options : 1.1, 1.4
Quick Review
This feature is only applicable to multiprocessor motherboards as it specifies the version of the Multi-Processor Specification (MPS) that the motherboard will use. The MPS is a specification by which PC manufacturers design and build Intel architecture systems with two or more processors.
MPS 1.1 was the original specification. MPS version 1.4 adds extended configuration tables for improved support of multiple PCI bus configurations and greater expandability in the future. In addition, MPS 1.4 introduces support for a secondary PCI bus without requiring a PCI bridge.
If your operating system comes with support for MPS 1.4, you should change the setting from the default of 1.1 to 1.4. You also need to enable MPS 1.4 support if you need to make use of the secondary PCI bus on a motherboard that doesn’t come with a PCI bridge.
You should only leave it as 1.1 only if you are running an older operating system that only supports MPS 1.1.
According to Eugene Tan, Windows NT already supports MPS 1.4. Therefore, newer operating systems like Windows 2000 and Windows XP shouldn’t have any problem supporting MPS 1.4.
However, users of the ABIT BP6 motherboard and Windows 2000 should take note of a possible problem with the MPS version set to 1.4. Dan Isaacs reported that when you set the MPS version to 1.4 in the ABIT BP6, Windows 2000 will not use the second processor. So, if you encounter this problem, set the MPS Version Control For OS to 1.1.
MPS Revision
Common Options : 1.1, 1.4
Quick Review
This feature is only applicable to multiprocessor motherboards as it specifies the version of the Multi-Processor Specification (MPS) that the motherboard will use. The MPS is a specification by which PC manufacturers design and build Intel architecture systems with two or more processors.
MPS 1.1 was the original specification. MPS version 1.4 adds extended configuration tables for improved support of multiple PCI bus configurations and greater expandability in the future. In addition, MPS 1.4 introduces support for a secondary PCI bus without requiring a PCI bridge.
If your operating system comes with support for MPS 1.4, you should change the setting from the default of 1.1 to 1.4. You also need to enable MPS 1.4 support if you need to make use of the secondary PCI bus on a motherboard that doesn’t come with a PCI bridge.
You should only leave it as 1.1 only if you are running an older operating system that only supports MPS 1.1.
According to Eugene Tan, Windows NT already supports MPS 1.4. Therefore, newer operating systems like Windows 2000 and Windows XP shouldn’t have any problem supporting MPS 1.4.
However, users of the ABIT BP6 motherboard and Windows 2000 should take note of a possible problem with the MPS version set to 1.4. Dan Isaacs reported that when you set the MPS version to 1.4 in the ABIT BP6, Windows 2000 will not use the second processor. So, if you encounter this problem, set the MPS Revision to 1.1.
PIRQ x Use IRQ No.
Common Options : Auto, 3, 4, 5, 7, 9, 10, 11, 12, 14, 15
Quick Review
This BIOS feature allows you to manually set the IRQ for a particular device installed on the AGP and PCI buses.
It is especially useful when you are transferring a hard disk from one computer to another; and you don’t want to reinstall your operating system to redetect the IRQ settings. By setting the IRQs to fit the original settings, you can circumvent a lot of configuration problems after installing the hard disk in a new system. However, this is only true for non-ACPI systems. ACPI systems need not to bother with this BIOS feature.
In most cases, you should just leave the setting as Auto. This allows the motherboard to assign the IRQs automatically. But if you need to assign a particular IRQ to a device on the AGP or PCI bus, here is how you can make use of this BIOS feature.
1. Determine the slot that the device is located in.
2. Check your motherboard’s PIRQ table (in the manual) to determine the slot’s primary PIRQ.
3. You can then select the IRQ you want by assigning the IRQ to the appropriate PIRQ.
Just remember that the BIOS will always try to allocate the PIRQ linked to INT A for each slot. It is just a matter of linking the IRQ you want to the correct PIRQ for that slot.
PNP OS Installed
Common Options : Yes, No
Quick Review
What this BIOS feature actually does is determine what devices are configured by the BIOS when the computer boots up and what are left to the operating system.
Non-ACPI BIOSes are found in older motherboards that do not support the new ACPI (Advanced Configuration and Power Interface) initiative. With such a BIOS, setting the PNP OS Installed feature to No allows the BIOS to configure all devices under the assumption that the operating system cannot do so. Therefore, all hardware settings are fixed by the BIOS at boot up and will not be changed by the operating system.
On the other hand, if you set the feature to Yes, the BIOS will only configure critical devices that are required to boot up the system. The other devices are then configured by the operating system. This allows the operating system some flexibility in shuffling system resources like IRQs and IO ports to avoid conflicts. It also gives you some degree of freedom when you want to manually assign system resources.
Of course, all current motherboards now ship with the new ACPI BIOS. If you are using an ACPI-compliant operating system (i.e. Windows 98 and above) with an ACPI BIOS, then this PNP OS Installed feature is no longer relevant. This is because the operating system will use the ACPI BIOS interface to configure all devices as well as retrieve system information.
But if your operating system does not support ACPI, then the BIOS will fall back to PNP mode. In this situation, consider the BIOS as you would a Non-ACPI BIOS. If there is no need to configure any hardware manually, it is again recommended that you set this feature to No.
For Linux users, Jonathan has the following advice –
Although Linux is not really PnP-compatible, most distributions use a piece of software called ISAPNPTOOLS to setup ISA cards. If you have PnP OS set to No, the BIOS will attempt to configure ISA cards itself. This does not make them work with Linux, though, you still need to use something like ISAPNPTOOLS. However, having both the BIOS and ISAPNPTOOLS attempting to configure ISA cards can lead to problems where the two don’t agree.
The solution? Set PnP OS to Yes, and let ISAPNPTOOLS take care of ISA cards in Linux, as BIOS configuration of ISA cards doesn’t work for Linux anyway (with the current stable and development kernels). Most times, it probably won’t make a difference, but someone somewhere will have problems, and Linux will always work with PnP OS set to Yes.
Britt Turnbull recommends disabling this feature if you are running the OS/2 operating system, especially in a multi-boot system. This is because booting another operating system can update the BIOS which may later cause problems when you boot up OS/2.
To sum it all up, except for certain cases, it is highly recommended that you to set this BIOS feature to No, irrespective of the operating system you actually use. Exceptions to this would be the inability of the BIOS to configure the devices properly in PnP mode and a specific need to manually configure one or more of the devices.

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